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data sheet march 2000 dsp1629 digital signal processor 1 features n optimized for digital cellular applications with a bit manipulation unit for higher coding efficiency. n on-chip, programmable, pll clock synthesizer. n 10 ns and 16.7 ns instruction cycle times at 3.0 v, and 19.2 ns and 12.5 ns instruction cycle times at 2.7 v, respectively. n mask-programmable memory map option: the dsp1629x16 features 16 kwords on-chip dual-port ram. the dsp1629x10 features 10 kwords on-chip dual-port ram. both feature 48 kwords on-chip rom with a secure option. n low power consumption: <1.9 mw/mips typical at 2.7 v. n flexible power management modes: standard sleep: 0.2 mw/mips at 2.7 v. sleep with slow internal clock: 0.7 mw at 2.7 v. hardware stop (pin halts dsp): <20 m a. n mask-programmable clock options: small signal, and cmos. n 144 pbga package (13 mm x 13 mm) available. n sequenced accesses to x and y external memory. n object code and pin compatible with the dsp1627. n single-cycle squaring. n 16 x 16-bit multiplication and 36-bit accumulation in one instruction cycle. n instruction cache for high-speed, program-efficient, zero-overhead looping. n dual 25 mbits/s serial i/o ports with multiprocessor capability: 16-bit data channel, 8-bit protocol channel. n 8-bit parallel host interface: supports 8- or 16-bit transfers. motorola * or intel ? compatible. n 8-bit control i/o interface. n 256 memory-mapped i/o ports. n ieee ? p1149.1 test port (jtag boundary scan). n full-speed in-circuit emulation hardware develop- ment system on-chip. n supported by dsp1629 software and hardware development tools. 2 description the dsp1629 is lucent technologies microelectronics groups first digital signal processor offering 100 mips operation at 3.0 v and 80 mips operation at 2.7 v with a reduction in power consumption. designed specifically for applications requiring low power dissipation in digital cellular systems, the dsp1629 is a signal-coding device that can be programmed to perform a wide variety of fixed-point signal processing functions. the device is based on the dsp1600 core with a bit manipulation unit for enhanced signal coding efficiency. the dsp1629 in- cludes a mix of peripherals specifically intended to sup- port processing-intensive but cost-sensitive applications in the area of digital wireless communications. the dsp1629x16 contains 16 kwords of internal dual- port ram (dpram), which allows simultaneous access to two ram locations in a single instruction cycle. the dsp1629x10 supports the use of 10 kwords of dpram. both devices contain 48 kwords of internal rom (irom). the dsp1629 is object code compatible with the dsp1627 while providing more memory. the dsp1629 is pin compatible with the dsp1627. note that trst (jtag test reset) replaces a v dd pin. the dsp1629 supports 2.7 v, and 3.0 v operation and flexible power management modes required for portable cellular terminals. several control mechanisms achieve low-power operation, including a stop pin for placing the dsp into a fully static, halted state and a programmable power control register used to power down unused on- chip i/o units. these power management modes allow for trade-offs between power reduction and wake-up la- tency requirements. during system standby, power con- sumption is reduced to less than 20 m a. the on-chip clock synthesizer can be driven by an exter- nal clock whose frequency is a fraction of the instruction rate. the device is packaged in a 144-pin pbga, a 100-pin bqfp, or a 100-pin tqfp and is available with 10 ns and 16.7 ns instruction cycle times at 3.0 v, and 19.2 ns and 12.5 ns instruction cycle times at 2.7 v, respectively. * motorola is a registered trademark of motorola, inc. ? intel is a registered trademark of intel corporation. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
data sheet dsp1629 digital signal processor march 2000 2 lucent technologies inc. table of contents contents page contents page 1 features.............................................................. 1 2 description .......................................................... 1 3 pin information.................................................... 3 4 hardware architecture ........................................ 8 4.1 dsp1629 architectural overview ............. 8 4.2 dsp1600 core architectural overview .. 11 4.3 interrupts and trap ................................. 12 4.4 memory maps and wait-states .............. 17 4.5 external memory interface (emi)............ 20 4.6 bit manipulation unit (bmu) ................... 21 4.7 serial i/o units (sios) ............................ 21 4.8 parallel host interface (phif)................. 23 4.9 bit input/output unit (bio)...................... 24 4.10 timer ...................................................... 25 4.11 jtag test port....................................... 25 4.12 clock synthesis ...................................... 27 4.13 power management ............................... 30 5 software architecture ....................................... 37 5.1 instruction set......................................... 37 5.2 register settings .................................... 46 5.3 instruction set formats .......................... 56 6 signal descriptions ........................................... 62 6.1 system interface..................................... 62 6.2 external memory interface ..................... 64 6.3 serial interface #1 .................................. 65 6.4 parallel host interface or serial interface #2 and control i/o interface .... 66 6.5 control i/o interface ............................... 66 6.6 jtag test interface ............................... 67 7 mask-programmable options ........................... 68 7.1 input clock options ................................ 68 7.2 memory map options ............................. 68 7.3 rom security options............................ 68 8 device characteristics ...................................... 69 8.1 absolute maximum ratings.................... 69 8.2 handling precautions.............................. 69 8.3 recommended operating conditions..... 69 8.4 package thermal considerations........... 70 9 electrical characteristics and requirements .... 71 9.1 power dissipation ................................... 74 10 timing characteristics for 3.0 v operation ....... 76 10.1 dsp clock generation............................ 77 10.2 reset circuit ........................................... 78 10.3 reset synchronization............................ 79 10.4 jtag i/o specifications.......................... 80 10.5 interrupt .................................................. 81 10.6 bit input/output (bio) ............................. 82 10.7 external memory interface...................... 83 10.8 phif specifications ................................ 87 10.9 serial i/o specifications.......................... 93 10.10 multiprocessor communication .............. 98 11 timing characteristics for 2.7 v operation ....... 99 11.1 dsp clock generation.......................... 100 11.2 reset circuit ......................................... 101 11.3 reset synchronization.......................... 102 11.4 jtag i/o specifications........................ 103 11.5 interrupt ................................................ 104 11.6 bit input/output (bio) ........................... 105 11.7 external memory interface.................... 106 11.8 phif specifications .............................. 110 11.9 serial i/o specifications........................ 116 11.10 multiprocessor communication ............ 121 12 outline diagrams ............................................ 122 12.1 100-pin bqfp (bumpered quad flat pack).............................................. 122 12.2 100-pin tqfp (thin quad flat pack)..................................................... 123 12.3 144-pin pbga (plastic ball grid array) .................................................... 124
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 3 3 pin information figure 1. dsp1629 bqfp pin diagram dsp1629 20 9 30 90 80 70 v ss sync1 do1 old1 ock1 ick1 ild1 v ss di1 v dd ibf1 obe1 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 v dd v ss db4 db2 db1 db0 v ss io db3 v ss v dd ab11 ab10 ab9 ab8 ab7 v ss eramhi erom rwn exm ab14 ab12 eramlo v dd sadd1 doen1 ock2/pcsn do2/pstat sync2/pbsel ild2/pids old2/pods ibf2/pibf obe2/pobe di2/pb1 v ss doen2/pb2 sadd2/pb3 trst iobit0/pb4 iobit1/pb5 iobit2/pb6 iobit3/pb7 vec3/iobit4 vec2/iobit5 vec1/iobit6 vec0/iobit7 v ss ick2/pb0 v ssa cki2 cki v dda tdo tms v dd cko trap stop iack v ss int0 int1 ab0 ab1 ab2 ab3 ab4 ab5 ab6 rstb tck 100 v dd 60 50 40 pin #1 identifier zone tdi ab13 v dd ab15 10 11 12 13 8 7 6 5 4 3 2 1 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 41 42 43 44 45 46 47 48 49 51 52 53 54 55 56 57 58 59 61 62 63 64 65 66 67 68 69 71 72 73 74 75 76 77 78 79 81 82 83 84 85 86 87 88 89 91 92 93 94 95 96 97 98 99 5-4218 (f).c
data sheet dsp1629 digital signal processor march 2000 4 lucent technologies inc. 3 pin information (continued) figure 2. dsp1629 tqfp pin diagram v dd db5 db6 db7 db8 db9 db10 v ss db11 db12 db13 db14 db15 v dd obe1 ibf1 v ss di1 ild1 ick1 ock1 old1 do1 sync1 v ss 100 90 80 v dd ab6 ab5 ab4 ab3 ab2 ab0 int1 int0 v ss iack stop trap rstb cko v dd tck tms tdo tdi v dda cki cki2 v ssa ab1 30 40 50 60 70 v dd sadd1 doen1 ock2/pcsn do2/pstat sync2/pbsel ild2/pids old2/pods ibf2/pibf obe2/pobe ick2/pb0 v ss doen2/pb2 sadd2/pb3 trst iobit0/pb4 iobit1/pb5 iobit2/pb6 iobit3/pb7 vec3/iobit4 vec2/iobit5 vec1/iobit6 vec0/iobit7 v ss di2/pb1 v ss db4 db3 db2 db1 db0 io eramhi v dd eramlo erom rwn v ss exm ab15 ab14 v dd ab13 ab12 ab11 ab10 ab9 ab8 ab7 v ss 1 10 20 dsp1629 71 72 73 74 75 61 62 63 64 65 66 67 68 69 76 77 78 79 59 58 57 56 55 54 53 52 51 41 42 43 44 45 46 47 48 49 31 32 33 34 35 36 37 38 39 29 28 27 26 21 22 23 24 25 11 12 13 14 15 16 17 18 19 2 3 4 5 6 7 8 9 81 82 83 84 85 86 87 88 89 91 92 93 94 95 96 97 98 99 5-4219 (f).c
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 5 3 pin information (continued) note: solder balls viewed through package. figure 3. 144-pin plastic ball grid array (top view) 5-5224 (c) v dda v ssa v dd v ss spare package balls should be tied to "soft gnd" or "sig gnd" m l k j h g f e d c b a 123456789101112
data sheet dsp1629 digital signal processor march 2000 6 lucent technologies inc. 3 pin information (continued) functional descriptions of pins 1100 are found in section 6, signal descriptions. the functionality of cki and cki2 pins are mask-programmable (see section 7, mask-programmable options). input levels on all i and i/o type pins are designed to remain at full cmos levels when not driven by the dsp. * 3-states when rstb = 0, or by jtag control. ? 3-states when rstb = 0 and int0 = 1. output = 1 when rstb = 0 and int0 = 0, except cko which is free-running. ? pull-up devices on input. 3-states by jtag control. ** see section 7, mask-programmable options. ?? for sio multiprocessor applications, add 5 k w external pull-up resistors to sadd1 and/or sadd2 for proper initialization. table 1. pin descriptions pbga pin bqfp pin tqfp pin symbol type name/function b6, a6, b5, a5, b4, a4, b3, a3, b2, a2, a1, b1, c2, c1, c3, d1 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 15, 16, 17, 18, 19 88, 89, 90, 91, 92, 94, 95, 96, 97, 98, 99, 2, 3, 4, 5, 6 db[15:0] i/o* external memory data bus 150. d2 20 7 io o ? data address 0x4000 to 0x40ff i/o enable. e1 21 8 eramhi o ? data address 0x8000 to 0xffff external ram enable. e2 23 10 eramlo o ? data address 0x4100 to 0x7fff external ram enable. f1 24 11 erom o ? program address external rom enable. f2 25 12 rwn o ? read/write not. g1 27 14 exm i external rom enable. g2, h1, h2, j1, j2, k1, k2, l1, l2, m1, k3, m2, l3, m3, l4, m4 28, 29, 31, 32, 33, 34, 35, 36, 37, 40, 41, 42, 43, 44, 45, 46 15, 16, 18, 19, 20, 21, 22, 23, 24, 27, 28, 29, 30, 31, 32, 33 ab[15:0] o* external memory address bus 150. l5 47 34 int1 i vectored interrupt 1. m5 48 35 int0 i vectored interrupt 0. l6 50 37 iack o* interrupt acknowledge. m6 51 38 stop i stop input clock. l7 52 39 trap i/o* nonmaskable program trap/breakpoint indication. m7 53 40 rstb i reset bar. l8 54 41 cko o ? processor clock output. m8 56 43 tck i jtag test clock. l9 57 44 tms i ? jtag test mode select. m9 58 45 tdo o jtag test data output. l10 59 46 tdi i ? jtag test data input. mask-programmable input clock option cmos small signal l11 61 48 cki** i cki vac m11 62 49 cki2** i v ssa vcm k10 65 52 vec0/iobit7 i/o* vectored interrupt indication 0/status/control bit 7. l12 66 53 vec1/iobit6 i/o* vectored interrupt indication 1/status/control bit 6. k11 67 54 vec2/iobit5 i/o* vectored interrupt indication 2/status/control bit 5. k12 68 55 vec3/iobit4 i/o* vectored interrupt indication 3/status/control bit 4. j11 69 56 iobit3/pb7 i/o* status/control bit 3/phif data bus bit 7. j12 70 57 iobit2/pb6 i/o* status/control bit 2/phif data bus bit 6. h11 71 58 iobit1/pb5 i/o* status/control bit 1/phif data bus bit 5. h12 72 59 iobit0/pb4 i/o* status/control bit 0/phif data bus bit 4. g11 73 60 trst i ? jtag test reset.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 7 3 pin information (continued) functional descriptions of pins 1100 are found in section 6, signal descriptions. * 3-states when rstb = 0, or by jtag control. ? 3-states when rstb = 0 and int0 = 1. output = 1 when rstb = 0 and int0 = 0, except cko which is free-running. ? pull-up devices on input. 3-states by jtag control. ** see section 7, mask-programmable options. ?? for sio multiprocessor applications, add 5 k w external pull-up resistors to sadd1 and/or sadd2 for proper initialization. table 1. pin descriptions (continued) pbga pin bqfp pin tqfp pin symbol type name/function g12 74 61 sadd2/pb3 ?? i/o* sio2 multiprocessor address/phif data bus bit 3. f11 75 62 doen2/pb2 i/o* sio2 data output enable/phif data bus bit 2. f12 77 64 di2/pb1 i/o* sio2 data input/phif data bus bit 1. e11 78 65 ick2/pb0 i/o* sio2 input clock/phif data bus bit 0. e12 79 66 obe2/pobe o* sio2 output buffer empty/phif out- put buffer empty. d11 80 67 ibf2/pibf o* sio2 input buffer full/phif input buff- er full. d12 81 68 old2/pods i/o* sio2 output load/phif output data strobe. c11 82 69 ild2/pids i/o* sio2 input load/phif input data strobe. c12 83 70 sync2/pbsel i/o* sio2 multiprocessor synchronization/ phif byte select. c10 84 71 do2/pstat i/o* sio2 data output/phif status regis- ter select. b12 85 72 ock2/pcsn i/o* sio2 output clock/phif chip select not. b11 86 73 doen1 i/o* sio1 data output enable. a12 87 74 sadd1 ?? i/o* sio1 multiprocessor address. a11 90 77 sync1 i/o* sio1 multiprocessor synchronization. b10 91 78 do1 o* sio1 data output. a10 92 79 old1 i/o* sio1 output load. b9 93 80 ock1 i/o* sio1 output clock. a9 94 81 ick1 i/o* sio1 input clock. b8 95 82 ild1 i/o* sio1 input load. a8 96 83 di1 i sio1 data input. b7 98 85 ibf1 o* sio1 input buffer full. a7 99 86 obe1 o* sio1 output buffer empty. d4, d5, d6, d7, d8, e4, e5, e6, e7, e8, e9, f4, f5, f6, f7, f8, f9, g4, g5, g6, g7, g8, g9, h4, h5, h6, h7, h8, h9, j4, j5, j6, j7, j8, j9 6, 15, 26, 38, 49, 64, 76, 89, 97 93, 1, 13, 25, 36, 51, 63, 76, 84 v ss p ground. c4, c5, c6, c7, c8, d3, d9, d10, e3, e10, f3, f10, g3, g10, h3, h10, j3, j10, k4, k5, k6, k7, k8, k9 14, 22, 30, 39, 55, 88, 100 100, 9, 17, 26, 42, 75, 87 v dd p power supply. m10 60 47 v dda p analog power supply. m12 63 50 v ssa p analog ground. c9 no die connectunused.
data sheet dsp1629 digital signal processor march 2000 8 lucent technologies inc. 4 hardware architecture the dsp1629 device is a 16-bit, fixed-point program- mable digital signal processor (dsp). the dsp1629 consists of a dsp1600 core together with on-chip mem- ory and peripherals. added architectural features give the dsp1629 high program efficiency for signal coding applications. 4.1 dsp1629 architectural overview figure 4 shows a block diagram of the dsp1629. the following modules make up the dsp1629. dsp1600 core the dsp1600 core is the heart of the dsp1629 chip. the core contains data and address arithmetic units, and control for on-chip memory and peripherals. the core provides support for external memory wait-states and on-chip, dual-port ram and features vectored inter- rupts and a trap mechanism. dual-port ram (dpram) the dsp1629x16 contains 16 banks of zero wait-state memory and the dsp1629x10 contains 10 banks of zero wait-state memory. each bank consists of 1k 16-bit words and has separate address and data ports to the instruction/coefficient and data memory spaces. a program can reference memory from either space. the dsp1600 core automatically performs the required multiplexing. if references to both ports of a single bank are made simultaneously, the dsp1600 core automati- cally inserts a wait-state and performs the data port ac- cess first, followed by the instruction/coefficient port access. a program can be downloaded from slow, off-chip mem- ory into dpram, and then executed without wait-states. dpram is also useful for improving convolution perfor- mance in cases where the coefficients are adaptive. since dpram can be downloaded through the jtag port, full-speed remote in-circuit emulation is possible. dpram can also be used for downloading self-test code via the jtag port. read-only memory (rom) the dsp1629 contains 48k 16-bit words of zero wait- state mask-programmable rom for program and fixed coefficients. external memory multiplexer (emux) the emux is used to connect the dsp1629 to external memory and i/o devices. it supports read/write opera- tions from/to instruction/coefficient memory (x memory space) and data memory (y memory space). the dsp1600 core automatically controls the emux. in- structions can transparently reference external memory from either set of internal buses. a sequencer allows a single instruction to access both the x and the y exter- nal memory spaces. clock synthesis the dsp powers up with a 1x input clock (cki/cki2) as the source for the processor clock. an on-chip clock synthesizer (pll) can also be used to generate the sys- tem clock for the dsp, which will run at a frequency mul- tiple of the input clock. the clock synthesizer is deselected and powered down on reset. for low-power operation, an internally generated slow clock can be used to drive the dsp. if both the clock synthesizer and the internally generated slow clock are selected, the slow clock will drive the dsp; however, the synthesizer will continue to run. the clock synthesizer and other programmable clock sources are discussed in section 4.12. the use of these programmable clock sources for power management is discussed in section 4.13. bit manipulation unit (bmu) the bmu extends the dsp1600 core instruction set to provide more efficient bit operations on accumulators. the bmu contains logic for barrel shifting, normaliza- tion, and bit field insertion/extraction. the unit also con- tains a set of 36-bit alternate accumulators. the data in the alternate accumulators can be shuffled with the data in the main accumulators. flags returned by the bmu mesh seamlessly with the dsp1600 conditional instruc- tions. bit input/output (bio) the bio provides convenient and efficient monitoring and control of eight individually configurable pins. when configured as outputs, the pins can be individually set, cleared, or toggled. when configured as inputs, individ- ual pins or combinations of pins can be tested for pat- terns. flags returned by the bio mesh seamlessly with conditional instructions. serial input/output units (sio and sio2) sio and sio2 offer asynchronous, full-duplex, double- buffered channels that operate at up to 25 mbits/s (for 20 ns instruction cycle in a nonmultiprocessor configu- ration), and easily interface with other lucent technol- ogies fixed-point dsps in a multiple-processor environment. commercially available codecs and time- division multiplex (tdm) channels can be interfaced to the serial i/o ports with few, if any, additional compo- nents. sio2 is identical to sio.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 9 4 hardware architecture (continued) an 8-bit serial protocol channel may be transmitted in addition to the address of the called processor in multiproces- sor mode. this feature is useful for transmitting high-level framing information or for error detection and correction. sio2 and bio are pin-multiplexed with the phif. * these registers are accessible through the pins only. ? 16k x 16 for the dsp1629x16, 10k x 16 for the dsp1629x10. figure 4. dsp1629 block diagram tdo tck tms m u x dsp1600 core rwn exm erom eramhi ab[15:0] db[15:0] i/o vec[3:0] or iobit[7:4] do2 or pstat old2 or pods ock2 or pcsn obe2 or pobe sync2 or pbsel ick2 or pb0 ild2 or pids di2 or pb1 ibf2 or pibf doen2 or pb2 sadd2 or pb3 io bit[3:0] or pb[7:4] cki cki2 cko rstb stop trap int[1:0] iack di1 ick1 ild1 ibf1 do1 ock1 old1 obe1 sync1 sadd1 doen1 external memory interface & emux ioc dual-port ram 16k/10k x 16 ? rom 48k x 16 eramlo yab ydb xdb xab bmu aa0 aa1 ar0 ar1 ar2 ar3 idb phif phifc pstat * pdx0(in) pdx0(out) bio sbit cbit sio2 sdx2(out) srta2 tdms2 sdx2(in) sioc2 saddx2 sio sdx(out) srta tdms sdx(in) sioc saddx timer timerc timer0 hds breakpoint * jtag boundary scan * jtag jcon * id * bypass * trace * powerc tdi pllc trst 5-4142 (f).f
data sheet dsp1629 digital signal processor march 2000 10 lucent technologies inc. 4 hardware architecture (continued) table 2. dsp1629 block diagram legend symbol name aa<01> alternate accumulators. ar<03> auxiliary bmu registers. bio bit input/output unit. bmu bit manipulation unit. breakpoint four instruction breakpoint registers. bypass jtag bypass register. cbit control register for bio. dual-port ram internal ram (16 kwords for dsp1629x16, 10 kwords for dsp1629x10). emux external memory multiplexer. hds hardware development system. id jtag device identification register. idb internal data bus. ioc i/o configuration register. jcon jtag configuration registers. jtag 16-bit serial/parallel register. pdx0(in) parallel data transmit input register 0. pdx0(out) parallel data transmit output register 0. phif parallel host interface. phifc parallel host interface control register. pllc phase-locked loop control register. powerc power control register. pstat parallel host interface status register. saddx multiprocessor protocol register. saddx2 multiprocessor protocol register for sio2. sbit status register for bio. sdx(in) serial data transmit input register. sdx2(in) serial data transmit input register for sio2. sdx(out) serial data transmit output register. sdx2(out) serial data transmit output register for sio2. sio serial input/output unit. sio2 serial input/output unit #2. sioc serial i/o control register. sioc2 serial i/o control register for sio2. srta serial receive/transmit address register. srta2 serial receive/transmit address register for sio2. tdms serial i/o time-division multiplex signal control register. tdms2 serial i/o time-division multiplex signal control register for sio2. timer programmable timer. timer0 timer running count register. timerc timer control register. trace program discontinuity trace buffer. xab program memory address bus. xdb program memory data bus. yab data memory address bus. ydb data memory data bus.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 11 4 hardware architecture (continued) parallel host interface (phif) the phif is a passive, 8-bit parallel port which can in- terface to an 8-bit bus containing other lucent technol- ogies dsps (e.g., dsp1620, dsp1627, dsp1628, dsp1629, dsp1611, dsp1616, dsp1617, dsp1618), microprocessors, or peripheral i/o devices. the phif port supports either motorola or intel protocols, as well as 8-bit or 16-bit transfers, configured in software. the port data rate depends upon the instruction cycle rate. a 25 ns instruction cycle allows the phif to support data rates up to 11.85 mbytes/s, assuming the external host device can transfer 1 byte of data in 25 ns. the phif is accessed in two basic modes: 8-bit or 16-bit mode. in 16-bit mode, the host determines an ac- cess of the high or low byte. in 8-bit mode, only the low byte is accessed. software-programmable features al- low for a glueless host interface to microprocessors (see section 4.8, parallel host interface). timer the timer can be used to provide an interrupt at the ex- piration of a programmed interval. the interrupt may be single or repetitive. more than nine orders of magnitude of interval selection are provided. the timer may be stopped and restarted at any time. hardware development system (hds) module the on-chip hds performs instruction breakpointing and branch tracing at full speed without additional off- chip hardware. using the jtag port, the breakpointing is set up, and the trace history is read back. the port works in conjunction with the hds code in the on-chip rom and the hardware and software in a remote com- puter. the hds code must be linked to the user's appli- cation code and reside in the first 4 kwords of rom. the on-chip hds cannot be used with the secure rom masking option (see section 7.3, rom security op- tions). four hardware breakpoints can be set on instruction ad- dresses. a counter can be preset with the number of breakpoints to receive before trapping the core. break- points can be set in interrupt service routines. alternate- ly, the counter can be preset with the number of cache instructions to execute before trapping the core. every time the program branches instead of executing the next sequential instruction, the addresses of the in- structions executed before and after the branch are caught in circular memory. the memory contains the last four pairs of program discontinuities for hardware tracing. in systems with multiple processors, the processors may be configured such that any processor reaching a breakpoint will cause all the other processors to be trapped (see section 4.3, interrupts and trap). pin multiplexing in order to allow flexible device interfacing while main- taining a low package pin count, the dsp1629 multi- plexes 16 package pins between bio, phif, vec[3:0], and sio2. upon reset, the vectored interrupt indication signals, vec[3:0], are connected to the package pins while iobit[4:7] are disconnected. setting bit 12, ebioh, of the ioc register connects iobit[4:7] to the package pins and disconnects vec[3:0]. upon reset, the parallel host interface (phif) is con- nected to the package pins while the second serial port (sio2) and iobit[3:0] are disconnected. setting bit 10, esio2, of the ioc register connects the sio2 and iobit[3:0] and disconnects the phif. power management many applications, such as portable cellular terminals, require programmable sleep modes for power manage- ment. there are three different control mechanisms for achieving low-power operation: the powerc control register, the stop pin, and the await bit in the alf reg- ister. the await bit in the alf register allows the proces- sor to go into a power-saving standby mode until an interrupt occurs. the powerc register configures various power-saving modes by controlling internal clocks and peripheral i/o units. the stop pin controls the internal processor clock. the various power management op- tions may be chosen based on power consumption and/ or wake-up latency requirements. 4.2 dsp1600 core architectural overview figure 5 shows a block diagram of the dsp1600 core. system cache and control section (sys) this section of the core contains a 15-word cache mem- ory and controls the instruction sequencing. it handles vectored interrupts and traps, and also provides decod- ing for registers outside of the dsp1600 core. sys stretches the processor cycle if wait-states are required (wait-states are programmable for external memory ac- cesses). sys sequences downloading via jtag of self- test programs to on-chip, dual-port ram. the cache loop iteration count can be specified at run time under program control as well as at assembly time.
data sheet dsp1629 digital signal processor march 2000 12 lucent technologies inc. 4 hardware architecture (continued) data arithmetic unit (dau) the data arithmetic unit (dau) contains a 16 x 16-bit parallel multiplier that generates a full 32-bit product in one instruction cycle. the product can be accumulated with one of two 36-bit accumulators. the accumulator data can be directly loaded from, or stored to, memory in two 16-bit words with optional saturation on overflow. the arithmetic logic unit (alu) supports a full set of arithmetic and logical operations on either 16- or 32-bit data. a standard set of flags can be tested for condition- al alu operations, branches, and subroutine calls. this procedure allows the processor to perform as a power- ful 16- or 32-bit microprocessor for logical and control applications. the available instruction set is fully com- patible with the dsp1627 instruction set. see section 5.1 for more information on the instruction set. the user also has access to two additional dau regis- ters. the psw register contains status information from the dau (see table 26, processor status word regis- ter). the arithmetic control register, auc, is used to con- figure some of the features of the dau (see table 27) including single-cycle squaring. the auc register align- ment field supports an arithmetic shift left by one and left or right by two. the auc register is cleared by reset. the counters c0 to c2 are signed, 8 bits wide, and may be used to count events such as the number of times the program has executed a sequence of code. they are controlled by the conditional instructions and pro- vide a convenient method of program looping. y space address arithmetic unit (yaau) the yaau supports high-speed, register-indirect, com- pound, and direct addressing of data (y) memory. four general-purpose, 16-bit registers, r0 to r3, are available in the yaau. these registers can be used to supply the read or write addresses for y space data. the yaau also decodes the 16-bit data memory address and out- puts individual memory enables for the data access. the yaau can address the six 1 kword banks of on- chip dpram or three external data memory segments. up to 48 kwords of off-chip ram are addressable, with 16k addresses reserved for internal ram. two 16-bit registers, rb and re, allow zero-overhead modulo addressing of data for efficient filter implemen- tations. two 16-bit signed registers, j and k, are used to hold user-defined postmodification increments. fixed increments of +1, C1, and +2 are also available. four compound-addressing modes are provided to make read/write operations more efficient. the yaau allows direct (or indexed) addressing of data memory. in direct addressing, the 16-bit base register (ybase) supplies the 11 most significant bits of the ad- dress. the direct data instruction supplies the remaining 5 bits to form an address to y memory space and also specifies one of 16 registers for the source or destina- tion. x space address arithmetic unit (xaau) the xaau supports high-speed, register-indirect, in- struction/coefficient memory addressing with postmodi- fication of the register. the 16-bit pt register is used for addressing coefficients. the signed register i holds a user-defined postincrement. a fixed postincrement of +1 is also available. register pc is the program counter. registers pr and pi hold the return address for subroutine calls and interrupts, respectively. the xaau decodes the 16-bit instruction/coefficient ad- dress and produces enable signals for the appropriate x memory segment. the addressable x segments are 48 kwords of internal rom, up to 16 kwords of dpram for the dsp1629x16 or up to 10 kwords of dpram for the dsp1629x10, and external rom. the locations of these memory segments depend upon the memory map selected (see table 5). a security mode can be selected by mask option. this prevents unauthorized access to the contents of on-chip rom (see section 7, mask-programmable options). 4.3 interrupts and trap the dsp1629 supports prioritized, vectored interrupts and a trap. the device has eight internal hardware sources of program interrupt and two external interrupt pins. additionally, there is a trap pin and a trap signal from the hardware development system (hds). a soft- ware interrupt is available through the icall instruction. the icall instruction is reserved for use by the hds. each of these sources of interrupt and trap has a unique vector address and priority assigned to it. dsp16a in- terrupt compatibility is not maintained. the software interrupt and the traps are always enabled and do not have a corresponding bit in the ins register. other vectored interrupts are enabled in the inc register (see table 29, interrupt control (inc) register) and monitored in the ins register (see table 30, interrupt status (ins) register). when the dsp1629 goes into an interrupt or trap service routine, the iack pin is assert- ed. in addition, pins vec[3:0] encode which interrupt/ trap is being serviced. table 4 details the encoding used for vec[3:0].
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 13 4 hardware architecture (continued) figure 5. dsp1600 core block diagram psw (16) auc (16) control cache cloop (7) inc (16) ins (16) alf (16) mwait (16) sys xdb xab idb yab ydb r0 (16) r1 (16) r2 (16) r3 (16) j (16) k (16) re (16) yaau rb (16) adder mux cmp ybase (16) pc (16) pt (16) pi (16) i (16) adder xaau extract/sat x (16) yh (16) yl (16) 16 x 16 mpy p (32) shift (C2, 0, 1, 2) c0 (8) c2 (8) c1 (8) 16 alu/shift a0 (36) a1 (36) 36 32 mux dau mux C1, 0, 1, 2 bridge mux 1 pr (16) 5-1741 (f).b
data sheet dsp1629 digital signal processor march 2000 14 lucent technologies inc. 4 hardware architecture (continued) * f3 alu instructions with immediates require specifying the high half of the accumulators as a0h and a1h. table 3. dsp1600 core block diagram legend symbol name 16 x 16 mpy 16-bit x 16-bit multiplier. a0a1 accumulators 0 and 1 (16-bit halves specified as a0, a0l, a1, and a1l).* alf await, lowpr, flags. alu/shift arithmetic logic unit/shifter. auc arithmetic unit control. c0c2 counters 02. cloop cache loop count. cmp comparator. dau digital arithmetic unit. i increment register for the x address space. idb internal data bus. inc interrupt control. ins interrupt status. j increment register for the y address space. k increment register for the y address space. mux multiplexer. mwait external memory wait-states register. p product register (16-bit halves specified as p, pl). pc program counter. pi program interrupt return register. pr program return register. psw processor status word. pt x address space pointer. r0r3 y address space pointers. rb modulo addressing register (begin address). re modulo addressing register (end address). sys system cache and control section. x multiplier input register. xaau x space address arithmetic unit. xab x space address bus. xdb x space data bus. yaau y space address arithmetic unit. yab y space address bus. ydb y space data bus. ybase direct addressing base register. y dau register (16-bit halves specified as y, yl).
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 15 4 hardware architecture (continued) interruptibility vectored interrupts are serviced only after the execution of an interruptible instruction. if more than one vectored interrupt is asserted at the same time, the interrupts are serviced sequentially according to their assigned priori- ties. see table 4 for the priorities assigned to the vec- tored interrupts. interrupt service routines, branch and conditional branch instructions, cache loops, and in- structions that only decrement one of the ram pointers, r0 to r3 (e.g., *r3 - - - - - - - - ), are not interruptible. a trap is similar to an interrupt, but it gains control of the processor by branching to the trap service routine even when the current instruction is noninterruptible. it may not be possible to return to normal instruction execution from the trap service routine since the machine state cannot always be saved. in particular, program execu- tion cannot be continued from a trapped cache loop or interrupt service routine. while in a trap service routine, another trap is ignored. when set to 1, the status bits in the ins register indicate that an interrupt has occurred. the processor must reach an interruptible state (completion of an interrupt- ible instruction) before an enabled vectored interrupt will be acted on. an interrupt will not be serviced if it is not enabled. polled interrupt service can be implemented by disabling the interrupt in the inc register and then polling the ins register for the expected event. vectored interrupts tables 29 and 30 show the inc and ins registers. a logic 1 written to any bit of inc enables (or unmasks) the as- sociated interrupt. if the bit is cleared to a logic 0, the in- terrupt is masked. note that neither the software interrupt nor traps can be masked. the occurrence of an interrupt that is not masked will cause the program execution to transfer to the memory location pointed to by that interrupt's vector address, as- suming no other interrupt is being serviced (see table 4, interrupt vector table). the occurrence of an inter- rupt that is masked causes no automatic processor ac- tion, but will set the corresponding status bit in the ins register. if a masked interrupt occurs, it is latched in the ins register, but the interrupt is not taken. when un- latched, this latched interrupt will initiate automatic pro- cessor interrupt action. see the dsp1611/17/18/27 digital signal processor information manual for a more detailed description of the interrupts. signaling interrupt service status five pins of dsp1629 are devoted to signaling interrupt service status. the iack pin goes high while any inter- rupt or user trap is being serviced, and goes low when the ireturn instruction from the service routine is issued. four pins, vec[3:0], carry a code indicating which of the interrupts or trap is being serviced. table 4 contains the encodings used by each interrupt. traps due to hds breakpoints have no effect on either the iack or vec[3:0] pins. instead, they show the inter- rupt state or interrupt source of the dsp when the trap occurred. clearing interrupts the phif interrupts (pibf and pobe) are cleared by reading or writing the parallel host interface data trans- mit registers pdx0[in] and pdx0[out], respectively. the sio and sio2 interrupts (ibf, ibf2, obe, and obe2) are cleared one instruction cycle after reading or writ- ing the serial data registers, (sdx[in], sdx2[in], sdx[out], or sdx2[out]). to account for this added latency, the user must ensure that a single instruction (nop or any other valid dsp16xx instruction) follows the sdx regis- ter read or write instruction prior to exiting an interrupt service routine (via an ireturn or goto pi instruction) or before checking the ins register for the sio flag status. adding this instruction ensures that interrupts are not reported incorrectly following an ireturn or that stale flags are not read from the ins register. the jtag inter- rupt (jint) is cleared by reading the jtag register. three of the vectored interrupts are cleared by writing to the ins register. writing a 1 to the int0, int1, or time bits in the ins will cause the corresponding interrupt sta- tus bit to be cleared to a logic 0. the status bit for these vectored interrupts is also cleared when the ireturn in- struction is executed, leaving set any other vectored in- terrupts that are pending. traps the trap pin of the dsp1629 is a bidirectional signal. at reset, it is configured as an input to the processor. asserting the trap pin will force a user trap. the trap mechanism is used for two purposes. it can be used by an application to rapidly gain control of the processor for asynchronous time-critical event handling (typically for catastrophic error recovery). it is also used by the hds for breakpointing and gaining control of the processor. separate vectors are provided for the user trap (0x46) and the hds trap (0x3). traps are not maskable.
data sheet dsp1629 digital signal processor march 2000 16 lucent technologies inc. 4 hardware architecture (continued) table 4. interrupt vector table source vector priority vec[3:0] issued by no interrupt 0x0 software interrupt 0x2 1 0x1 icall int0 0x1 2 0x2 pin jint 0x42 3 0x8 jtag in int1 0x4 4 0x9 pin time 0x10 7 0xc timer ibf2 0x14 8 0xd sio2 in obe2 0x18 9 0xe sio2 out reserved 0x1c 10 0x0 reserved 0x20 11 0x1 reserved 0x24 12 0x2 ibf 0x2c 14 0x3 sio in obe 0x30 15 0x4 sio out pibf 0x34 16 0x5 phif in pobe 0x38 17 0x6 phif out trap from hds 0x3 18 * * traps due to hds breakpoints have no effect on vec[3:0] pins. breakpoint, jtag, or pin trap from user 0x46 19 = highest 0x7 pin a trap has four cycles of latency. at most, two instruc- tions will execute from the time the trap is received at the pin to when it gains control. an instruction that is ex- ecuting when a trap occurs is allowed to complete be- fore the trap service routine is entered. (note that the instruction could be lengthened by wait-states.) during normal program execution, the pi register contains ei- ther the address of the next instruction (two-cycle in- struction executing) or the address following the next instruction (one-cycle instruction executing). in an inter- rupt service routine, pi contains the interrupt return ad- dress. when a trap occurs during an interrupt service routine, the value of the pi register may be overwritten. specifically, it is not possible to return to an interrupt service routine from a user trap (0x46) service routine. continuing program execution when a trap occurs dur- ing a cache loop is also not possible. the hds trap causes circuitry to force the program memory map to map1 (with on-chip rom starting at ad- dress 0x0) when the trap is taken. the previous memo- ry map is restored when the trap service routine exits by issuing an ireturn. the map is forced to map1 because the hds code, if present, resides in the on-chip rom. using the lucent technologies development tools, the trap pin may be configured to be an output, or an input vectoring to address 0x3. in a multiprocessor environ- ment, the trap pins of all the dsps present can be tied together. during hds operations, one dsp is selected by the host software to be the master. the master pro- cessor's trap pin is configured to be an output. the trap pins of the slave processors are configured as inputs. when the master processor reaches a break- point, the master's trap pin is asserted. the slave pro- cessors will respond to their trap input by beginning to execute the hds code. await interrupt (standby or sleep mode) setting the await bit (bit 15) of the alf register (alf = 0x8000) causes the processor to go into a power-saving standby or sleep mode. only the minimum circuitry on the chip required to process an incoming interrupt re- mains active. after the await bit is set, one additional instruction will be executed before the standby power- saving mode is entered. a phif or sio word transfer will complete if already in progress. the await bit is re- set when the first interrupt occurs. the chip then wakes up and continues executing. two nop instructions should be programmed after the await bit is set. the first nop (one cycle) will be exe- cuted before sleeping; the second will be executed after the interrupt signal awakens the dsp and before the in- terrupt service routine is executed.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 17 4 hardware architecture (continued) the await bit should be set from within the cache if the code which is executing resides in external rom where more than one wait-state has been programmed. this ensures that an interrupt will not disturb the device from completely entering the sleep state. for additional power savings, set ioc = 0x0180 and tim- erc = 0x0040 in addition to setting alf = 0x8000. this will hold the cko pin low and shut down the timer and pres- caler (see table 38 and table 31). for a description of the control mechanisms for putting the dsp into low-power modes, see section 4.13, pow- er management. 4.4 memory maps and wait-states the dsp1600 core implements a modified harvard ar- chitecture that has separate on-chip 16-bit address and data buses for the instruction/coefficient (x) and data (y) memory spaces. table 5 shows the instruction/coef- ficient memory space maps for both the dsp1629x16 and dsp1629x10. the dsp1629 provides a multiplexed external bus which accesses external ram (eram) and rom (erom). programmable wait-states are provided for external memory accesses. the instruction/coefficient memory map is configurable to provide application flex- ibility. table 6 shows the data memory space, which has one map. instruction/coefficient memory map selection in determining which memory map to use, the proces- sor evaluates the state of two parameters. the first is the lowpr bit (bit 14) of the alf register. the lowpr bit of the alf register is initialized to 0 automatically at re- set. lowpr controls the starting address in memory assigned to 1k banks of dual-port ram. if lowpr is low, internal dual-port ram begins at address 0xc000. if lowpr is high, internal dual-port ram begins at ad- dress 0x0. lowpr also moves irom from 0x0 in map1 to 0x4000 in map3, and erom from 0x0 in map2 to 0x4000 in map4. the second parameter is the value at reset of the exm pin (pin 27 or pin 14, depending upon the package type). exm determines whether the internal 48 kwords rom (irom) will be addressable in the memory map. the lucent technologies development system tools, together with the on-chip hds circuitry and the jtag port, can independently set the memory map. specifi- cally, during an hds trap, the memory map is forced to map1. the user's map selection is restored when the trap service routine has completed execution. map1 map1 has the irom starting at 0x0 and 1 kword banks of dpram starting at 0xc000. map1 is used if dsp1629 has exm low at reset and the lowpr pa- rameter is programmed to zero. it is also used during an hds trap. map2 map2 differs from map1 in that the lowest 48 kwords reference external rom (erom). map2 is used if exm is high at reset, the lowpr parameter is programmed to zero, and an hds trap is not in progress. map3 map3 has the 1 kword banks of dpram starting at address 0x0. in map3, the 48 kwords of irom start at 0x4000. map3 is used if exm is low at reset, the low- pr bit is programmed to 1, and an hds trap is not in progress. note that this map is not available if the se- cure mask-programmable option has been ordered. map4 map4 differs from map3 in that addresses above 0x4000 reference external rom (erom). this map is used if the lowpr bit is programmed to 1, an hds trap is not in progress, and, either exm is high during reset, or the secure mask-programmable option has been or- dered. whenever the chip is reset using the rstb pin, the de- fault memory map will be map1 or map2, depending upon the state of the exm pin at reset. a reset through the hds will not reinitialize the alf register, so the previ- ous memory map is retained. boot from external rom after rstb goes from low to high, the dsp1629 comes out of reset and fetches an instruction from address zero of the instruction/coefficient space. the physical location of address zero is determined by the memory map in effect. if exm is high at the rising edge of rstb, map2 is selected. map2 has erom at location zero; thus, program execution begins from external memory. if exm is high and int1 is low when rstb rises, the mwait register defaults to 15 wait-states for all external memory segments. if int1 is high, the mwait register defaults to 0 wait-states.
data sheet dsp1629 digital signal processor march 2000 18 lucent technologies inc. 4 hardware architecture (continued) table 5. instruction/coefficient memory maps * map1 is set automatically during an hds trap. the user-selected map is restored at the end of the hds trap service routine. ? lowpr is an alf register bit. the lucent technologies development system tools can independently set the memory map. ? map3 is not available if the secure mask-programmable option is selected. dsp1629x16 x address ab[0:15] map 1 * exm = 0 lowpr = 0 ? map 2 exm = 1 lowpr = 0 map 3 ? exm = 0 lowpr = 1 map 4 exm = 1 lowpr = 1 0 0x0000 irom (48k) erom (48k) dpram (16k) dpram (16k) 4k 0x1000 6k 0x1800 12k 0x3000 16k 0x4000 irom (48k) erom (48k) 20k 0x5000 24k 0x6000 28k 0x7000 32k 0x8000 36k 0x9000 40k 0xa000 44k 0xb000 48k 0xc000 dpram (16k) dpram (16k) 52k 0xd000 54k 0xd800 56k 0xe000 60k64k 0xffff dsp1629x10 x address ab[0:15] map 1 * exm = 0 lowpr = 0 ? map 2 exm = 1 lowpr = 0 map 3 ? exm = 0 lowpr = 1 map 4 exm = 1 lowpr = 1 0 0x0000 irom (48k) erom (48k) dpram (10k) dpram (10k) 4k 0x1000 6k 0x1800 10k 0x2800 reserved (6k) reserved (6k) 12k 0x3000 16k 0x4000 irom (48k) erom (48k) 20k 0x5000 24k 0x6000 28k 0x7000 32k 0x8000 36k 0x9000 40k 0xa000 44k 0xb000 48k 0xc000 dpram (10k) dpram (10k) 52k 0xd000 54k 0xd800 56k 0xe000 58k 0xe800 reserved (6k) reserved (6k) 60k64k 0xffff
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 19 4 hardware architecture (continued) table 6. data memory maps on the data memory side (see table 6), the 1k banks of dual-port ram are located starting at address 0. ad- dresses from 0x4000 to 0x40ff reference a 256-word memory-mapped i/o segment (io). addresses from 0x4100 to 0x7fff reference the low external data ram segment (eramlo). addresses above 0x8000 refer- ence high external data ram (eramhi). wait-states the number of wait-states (from 0 to 15) used when ac- cessing each of the four external memory segments (eramlo, io, eramhi, and erom) is programmable in the mwait register (see table 36). when the program references memory in one of the four external seg- ments, the internal multiplexer is automatically switched to the appropriate set of internal buses, and the associ- ated external enable of eramlo, io, eramhi, or erom is issued. the external memory cycle is auto- matically stretched by the number of wait-states config- ured in the appropriate field of the mwait register. 1629x16 data memory map (not to scale) decimal address address in r0, r1, r2, r3 segment 0 0x0000 dpram[1:16] 16k 0x4000 io 16,640 0x4100 eramlo 32k 0x8000 eramhi 64k C 1 0xffff 1629x10 data memory map (not to scale) decimal address address in r0, r1, r2, r3 segment 0 0x0000 dpram[1:10] 10k 0x2800 reserved (6 k) 16k 0x4000 io 16,640 0x4100 eramlo 32k 0x8000 eramhi 64k C 1 0xffff
data sheet dsp1629 digital signal processor march 2000 20 lucent technologies inc. 4 hardware architecture (continued) 4.5 external memory interface (emi) the external memory interface supports read/write op- erations from instruction/coefficient memory, data memory, and memory-mapped i/o devices. the dsp1629 provides a 16-bit external address bus, ab[15:0], and a 16-bit external data bus, db[15:0]. these buses are multiplexed between the internal bus- es for the instruction/coefficient memory and the data memory. four external memory segment enables, eramlo, io, eramhi, and erom, select the external memory segment to be addressed. if a data memory location with an address between 0x4100 and 0x7fff is addressed, eramlo is asserted low. if one of the 256 external data memory locations, with an address greater than or equal to 0x4000, and less than or equal to 0x40ff, is addressed, io is asserted low. io is intended for memory-mapped i/o. if a data memory location with an address greater than or equal to 0x8000 is addressed, eramhi is asserted low. when the external instruction/coefficient memory is addressed, erom is asserted low. the flexibility provided by the programmable options of the external memory interface (see table 36, mwait register and table 38, ioc register) allows the dsp1629 to interface gluelessly with a variety of com- mercial memory chips. each of the four external memory segments, eramlo, io, eramhi, and erom, has a number of wait-states that is programmable (from 0 to 15) by writing to the mwait register. when the program references memory in one of the four external segments, the internal multi- plexer is automatically switched to the appropriate set of internal buses, and the associated external enable of eramlo, io, eramhi, or erom is issued. the exter- nal memory cycle is automatically stretched by the num- ber of wait-states in the appropriate field of the mwait register. when writing to external memory, the rwn pin goes low for the external cycle. the external data bus, db[15:0], is driven by the dsp1629 starting halfway through the cycle. the data driven on the external data bus is automatically held after the cycle for one addi- tional clock period unless an external read cycle imme- diately follows. the dsp1629 has one external address bus and one external data bus for both memory spaces. since some instructions provide the capability of simultaneous ac- cess to both x space and y space, some provision must be made to avoid collisions for external accesses. the dsp1629 has a sequencer that does the external x ac- cess first, and then the external y access, transparently to the programmer. wait-states are maintained as pro- grammed in the mwait register. for example, let two in- structions be executed: the first reads a coefficient from erom and writes data to eram; the second reads a coefficient from erom and reads data from eram. the sequencer carries out the following steps at the external memory interface: read erom, write eram, read er- om, and read eram. each step is done in sequential one-instruction cycle steps, assuming zero wait-states are programmed. note that the number of instruction cycles taken by the two instructions is four. also, in this case, the write hold time is zero. the dsp1629 allows writing into external instruction/ coefficient memory. by setting bit 11, werom, of the ioc register (see table 38), writing to (or reading from) data memory or memory-mapped i/o asserts the erom strobe instead of eramlo, io, or eramhi. therefore, with werom set, erom appears in both y space (replacing eram) and x space, in its normal po- sition. bit 14 of the ioc register (see table 38), extrom, may be used with werom to download to a full 64k of ex- ternal memory. when werom and extrom are both asserted, address bit 15 (ab15) is held low, aliasing the upper 32k of external memory into the lower 32k. when an access to internal memory is made, the ab[15:0] bus holds the last valid external memory ad- dress. asserting the rstb pin low 3-states the ab[15:0] bus. after reset, the ab[15:0] value is undefined. the leading edge of the memory segment enables can be delayed by approximately one-half a cko period by programming the ioc register (see table 38). this is used to avoid a situation in which two devices drive the data bus simultaneously. bits 7, 8, and 13 of the ioc register select the mode of operation for the cko pin (see table 38). available op- tions are a free-running unstretched clock, a wait-stated sequenced clock (runs through two complete cycles during a sequenced external memory access), and a wait-stated clock based on the internal instruction cycle. these clocks drop to the low-speed internal ring oscilla- tor when slowcki is enabled (see 4.13, power man- agement). the high-to-low transitions of the wait-stated clock are synchronized to the high-to-low transition of the free-running clock. also, the cko pin provides ei- ther a continuously high level, a continuously low level, or changes at the rate of the internal processor clock. this last option, only available with the small-signal in- put clock options, enables the dsp1629 cki input buff- er to deliver a full-rate clock to other devices while the dsp1629 itself is in one of the low-power modes.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 21 4 hardware architecture (continued) 4.6 bit manipulation unit (bmu) the bmu interfaces directly to the main accumulators in the dau providing the following features: n barrel shiftinglogical and arithmetic, left and right shift n normalization and extraction of exponent n bit-field extraction and insertion these features increase the efficiency of the dsp in ap- plications such as control or data encoding and decod- ing. for example, data packing and unpacking, in which short data words are packed into one 16-bit word for more efficient memory storage, is very easy. in addition, the bmu provides two auxiliary accumula- tors, aa0 and aa1. in one instruction cycle, 36-bit data can be shuffled, or swapped, between one of the main accumulators and one of the alternate accumulators. the ar<03> registers are 16-bit registers that control the operations of the bmu. they store a value that de- termines the amount of shift or the width and offset fields for bit extraction or insertion. certain operations in the bmu set flags in the dau psw register and the alf register (see table 26, processor status word (psw) register, and table 35, alf register). the ar<03> reg- isters can also be used as general-purpose registers. the bmu instructions are detailed in section 5.1. for a thorough description of the bmu, see the dsp1611/17/ 18/27 digital signal processor information manual . 4.7 serial i/o units (sios) the serial i/o ports on the dsp1629 device provide a serial interface to many codecs and signal processors with little, if any, external hardware required. each high- speed, double-buffered port (sdx and sdx2) supports back-to-back transmissions of data. sio and sio2 are identical. the output buffer empty (obe and obe2) and input buffer full (ibf and ibf2) flags facilitate the read- ing and/or writing of each serial i/o port by program- or interrupt-driven i/o. there are four selectable active clock speeds. a bit-reversal mode provides compatibility with either the most significant bit (msb) first or least significant bit (lsb) first serial i/o formats (see table 22, serial i/o control registers (sioc and sioc2)). a multiprocessor i/o configuration is supported. this feature allows up to eight dsp161x devices to be connected together on an sio port without requiring external glue logic. the serial data may be internally looped back by setting the sio loopback control bit, siolbc, of the ioc regis- ter. siolbc affects both the sio and sio2. the data output signals are wrapped around internally from the output to the input (do1 to di1 and do2 to di2). to ex- ercise loopback, the sio clocks (ick1, ick2, ock1, and ock2) should either all be in the active mode, 16-bit condition, or each pair should be driven from one external source in passive mode. similarly, pins ild1 (ild2) and old1 (old2) must both be in active mode or tied together and driven from one external frame clock in passive mode. during loopback, do1, do2, di1, di2, ick1, ick2, ock1, ock2, ild1, ild2, old1, old2, sadd1, sadd2, sync1, sync2, doen1, and doen2 are 3-stated. setting dodly = 1 (sioc and sioc2) delays do by one phase of ock so that do changes on the falling edge of ock instead of the rising edge (dodly = 0). this re- duces the time available for do to drive di and to be val- id for the rising edge of ick, but increases the hold time on do by half a cycle on ock. programmable modes programmable modes of operation for the sio and sio2 are controlled by the serial i/o control registers (sioc and sioc2). these registers, shown in table 22, are used to set the ports into various configurations. both input and output operations can be independently configured as either active or passive. when active, the dsp1629 generates load and clock signals. when pas- sive, load and clock signal pins are inputs. since input and output can be independently config- ured, each sio has four different modes of operation. each of the sioc registers is also used to select the fre- quency of active clocks for that sio. finally, these reg- isters are used to configure the serial i/o data formats. the data can be 8 or 16 bits long, and can also be input/ output msb first or lsb first. input and output data for- mats can be independently configured. multiprocessor mode the multiprocessor mode allows up to eight devices that support multiprocessor mode (codecs or dsp16xx devices) to be connected together to provide data trans- mission among any of the multiprocessor devices in the system. either of the dsp1629s sio ports (sio or sio2) may be independently used for the multiproces- sor mode. the multiprocessor interface is a four-wire in- terface, consisting of a data channel, an address/ protocol channel, a transmit/receive clock, and a sync signal (see figure 6). the di1 and do1 pins of all the dsps are connected to transmit and receive the data channel. the sadd1 pins of all the dsps are connect- ed to transmit and receive the address/protocol chan- nel. ick1 and ock1 should be tied together and driven from one source. the sync1 pins of all the dsps are connected.
data sheet dsp1629 digital signal processor march 2000 22 lucent technologies inc. 4 hardware architecture (continued) in the configuration shown in figure 6, the master dsp (dsp0) generates active sync1 and ock1 signals while the slave dsps use the sync1 and ock1 signals in passive mode to synchronize operations. in addition, all dsps must have their ild1 and old1 signals in ac- tive mode. while ild1 and old1 are not required externally for multiprocessor operation, they are used internally in the dsp's sio. setting the ld field of the master's sioc reg- ister to a logic level 1 will ensure that the active genera- tion of sync1, ild1, and old1 is derived from ock1 (see table 22). with this configuration, all dsps should use ick1 (tied to ock1) in passive mode to avoid con- flicts on the clock (ck) line (see the dsp1611/17/18/27 digital signal processor information manual for more information). four registers (per sio) configure the multiprocessor mode: the time-division multiplexed slot register (tdms or tdms2), the serial receive and transmit address reg- ister (srta or srta2), the serial data transmit register (sdx or sdx2), and the multiprocessor serial address/protocol register (saddx or saddx2). multiprocessor mode requires no external logic and uses a tdm interface with eight 16-bit time slots per frame. the transmission in any time slot consists of 16 bits of serial data in the data channel and 16 bits of address and protocol information in the address/proto- col channel. the address information consists of the transmit address field of the srta register of the transmit- ting device. the address information is transmitted con- currently with the transmission of the first 8 bits of data. the protocol information consists of the transmit proto- col field written to the saddx register and is transmitted concurrently with the last 8 bits of data (see table 25, multiprocessor protocol register). data is received or recognized by other dsp(s) whose receive address matches the address in the address/protocol channel. each sio port has a user-programmable receive ad- dress and transmit address associated with it. the transmit and receive addresses are programmed in the srta register. in multiprocessor mode, each device can send data in a unique time slot designated by the tdms register trans- mit slot field (bits 70). the tdms register has a fully de- coded transmit slot field in order to allow one dsp1629 device to transmit in more than one time slot. this pro- cedure is useful for multiprocessor systems with less than eight dsp1629 devices when a higher bandwidth is necessary between certain devices in that system. the dsp operating during time slot 0 also drives sync1. in order to prevent multiple bus drivers, only one dsp can be programmed to transmit in a particular time slot. in addition, it is important to note that the address/pro- tocol channel is 3-stated in any time slot that is not being driven. therefore, to prevent spurious inputs, the address/pro- tocol channel should be pulled up to v dd with a 5 k w re- sistor, or it should be guaranteed that the bus is driven in every time slot. (if the sync1 signal is externally gen- erated, then this pull-up is required for correct initializa- tion.) each sio also has a fully decoded transmitting address specified by the srta register transmit address field (bits 70). this is used to transmit information regarding the destination(s) of the data. the fully decoded receive ad- dress specified by the srta register receive address field (bits 158) determines which data will be received. the sio protocol channel data is controlled via the sad- dx register. when the saddx register is written, the lower 8 bits contain the 8-bit protocol field. on a read, the high-order 8 bits read from saddx are the most recently received protocol field sent from the transmitting dsp's saddx output register. the low-order 8 bits are read as 0s. an example use of the protocol channel is to use the top 3 bits of the saddx value as an encoded source address for the dsps on the multiprocessor bus. this leaves the remaining 5 bits available to convey additional control information, such as whether the associated field is an opcode or data, or whether it is the last word in a trans- fer, etc. these bits can also be used to transfer parity in- formation about the data. alternatively, the entire field can be used for data transmission, boosting the band- width of the port by 50%. using sio2 the sio2 functions the same as the sio. please refer to pin multiplexing in section 4.1 for a description of pin multiplexing of bio, phif, vec[3:0], and sio2.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 23 4 hardware architecture (continued) figure 6. multiprocessor communication and connections dsp 0 do ick sadd sync dsp 1 dsp 7 data channel clock address/protocol channel sync signal di ock do ick sadd sync di ock do ick sadd sync di ock 5 k w v dd 5-4181 (f).a 4.8 parallel host interface (phif) the dsp1629 has an 8-bit parallel host interface for rapid transfer of data with external devices. this parallel port is passive (data strobes provided by an external de- vice) and supports either motorola or intel microcontrol- ler protocols. the phif also provides for 8-bit or 16-bit data transfers. as a flexible host interface, it re- quires little or no glue logic to interface to other devices (e.g., microcontrollers, microprocessors, or another dsp). the data path of the phif consists of a 16-bit input buff- er, pdx0(in), and a 16-bit output buffer, pdx0(out). two output pins, parallel input buffer full (pibf) and parallel output buffer empty (pobe), indicate the state of the buffers. in addition, there are two registers used to con- trol and monitor the phif's operation: the parallel host interface control register (phifc, see table 28), and the phif status register (pstat, see table 8). the pstat register, which reflects the state of the pibf and pobe flags, can only be read by an external device when the pstat input pin is asserted. the phifc register defines the programmable options for this port. the function of the pins, pids and pods, is program- mable to support both the intel and motorola protocols. the pin, pcsn, is an input that, when low, enables pids and pods (or prwn and pds, depending on the protocol used). while pcsn is high, the dsp1629 ig- nores any activity on pids and/or pods. if a dsp1629 is intended to be continuously accessed through the phif port, pcsn should be grounded. if pcsn is low and their respective bits in the inc register are set, the assertion of pids and pods by an external device causes the dsp1629 device to recognize an interrupt. programmability the parallel host interface can be programmed for 8-bit or 16-bit data transfers using bit 0, pmode, of the phifc register. setting pmode selects 16-bit transfer mode. an input pin controlled by the host, pbsel, determines an access of either the high or low bytes. the assertion level of the pbsel input pin is configurable in software using bit 3 of the phifc register, pbself. table 7 sum- marizes the port's functionality as controlled by the pstat and pbsel pins and the pbself and pmode fields. for 16-bit transfers, if pbself is zero, the pibf and pobe flags are set after the high byte is transferred. if pbself is one, the flags are set after the low byte is transferred. in 8-bit mode, only the low byte is access- ed, and every completion of an input or output access sets pibf or pobe. bit 1 of the phifc register, pstrobe, configures the port to operate either with an intel protocol where only the chip select (pcsn) and either of the data strobes (pids or pods) are needed to make an access, or with a motorola protocol where the chip select (pcsn), a data strobe (pds), and a read/write strobe (prwn) are needed. pids and pods are negative assertion data strobes while the assertion level of pds is programma- ble through bit 2, pstrb, of the phifc register.
data sheet dsp1629 digital signal processor march 2000 24 lucent technologies inc. 4 hardware architecture (continued) finally, the assertion level of the output pins, pibf and pobe, is controlled through bit 4, pflag. when pflag is set low, pibf and pobe output pins have positive assertion levels. by setting bit 5, pflagsel, the logical or of pibf and pobe flags (positive assertion) is seen at the output pin pibf. by setting bit 7 in phifc, psobef, the po- larity of the pobe flag in the status register, pstat, can be changed. psobef has no effect on the pobe pin. pin multiplexing please refer to pin multiplexing in section 4.1 for a description of bio, phif, vec[3:0], and sio2 pins. table 7. phif function (8-bit and 16-bit modes) pmode field pstat pin pbsel pin pbself field = 0 pbself field = 1 0 (8-bit) 0 0 pdx0 low byte reserved 0 0 1 reserved pdx0 low byte 010 pstat reserved 0 1 1 reserved pstat 1 (16-bit) 0 0 pdx0 low byte pdx0 high byte 1 0 1 pdx0 high byte pdx0 low byte 110 pstat reserved 1 1 1 reserved pstat table 8. pstat register as seen on pb[7:0] bit 76543210 field rsvd pibf pobe 4.9 bit input/output unit (bio) the bio controls the directions of eight bidirectional control i/o pins, iobit[7:0]. if a pin is configured as an output, it can be individually set, cleared, or toggled. if a pin is configured as an input, it can be read and/or test- ed. the lower half of the sbit register (see table 33) con- tains current values (value[7:0]) of the eight bidirec- tional pins iobit[7:0]. the upper half of the sbit register (direc[7:0]) controls the direction of each of the pins. a logic 1 configures the corresponding pin as an output; a logic 0 configures it as an input. the upper half of the sbit register is cleared upon reset. the cbit register (see table 34) contains two 8-bit fields, mode/mask[7:0] and data/pat[7:0]. the values of data/pat[7:0] are cleared upon reset. the meaning of a bit in either field depends on whether it has been con- figured as an input or an output in sbit. if a pin has been configured to be an output, the meanings are mode and data. for an input, the meanings are mask and pat (pattern). table 9 shows the functionality of the mode/mask and data/pat bits based on the direc- tion selected for the associated iobit pin. those bits that have been configured as inputs can be individually tested for 1 or 0. for those inputs that are being tested, there are four flags produced: allt (all true), allf (all false), somet (some true), and somef (some false). these flags can be used for conditional branch or special instructions. the state of these flags can be saved and restored by reading and writing bits 0 to 3 of the alf register (see table 35). if a bio pin is switched from being configured as an out- put to being configured as an input and then back to be- ing configured as an output, the pin retains the previous output value. pin multiplexing please refer to pin multiplexing in section 4.1 for a description of bio, phif, vec[3:0], and sio2 pins. table 9. bio operations direc[n] * *0 n 7. mode/ mask[n] data/ pat[n] action 1 (output) 0 0 clear 1 (output) 0 1 set 1 (output) 1 0 no change 1 (output) 1 1 toggle 0 (input) 0 0 no test 0 (input) 0 1 no test 0 (input) 1 0 test for zero 0 (input) 1 1 test for one
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 25 4 hardware architecture (continued) 4.10 timer the interrupt timer is composed of the timerc (control) register, the timer0 register, the prescaler, and the counter itself. the timer control register (see table 31, timerc register) sets up the operational state of the tim- er and prescaler. the timer0 register is used to hold the counter reload value (or period register) and to set the initial value of the counter. the prescaler slows the clock to the timer by a number of binary divisors to allow for a wide range of interrupt delay periods. the counter is a 16-bit down counter that can be loaded with an arbitrary number from software. it counts down to 0 at the clock rate provided by the prescaler. upon reaching 0 count, a vectored interrupt to program ad- dress 0x10 is issued to the dsp1629, providing the in- terrupt is enabled (bit 8 of inc and ins registers). the counter will then either wait in an inactive state for an- other command from software, or will automatically re- peat the last interrupting period, depending upon the state of the reload bit in the timerc register. when reload is 0, the counter counts down from its initial value to 0, interrupts the dsp1629, and then stops, remaining inactive until another value is written to the timer0 register. writing to the timer0 register causes both the counter and the period register to be written with the specified 16-bit number. when reload is 1, the counter counts down from its initial value to 0, inter- rupts the dsp1629, automatically reloads the specified initial value from the period register into the counter, and repeats indefinitely. this provides for either a single timed interrupt event or a regular interrupt clock of arbi- trary period. the timer can be stopped and started by software, and can be reloaded with a new period at any time. its count value, at the time of the read, can also be read by soft- ware. due to pipeline stages, stopping and starting the timer may result in one inaccurate count or prescaled period. when the dsp1629 is reset, the bottom 6 bits of the timerc register and the timer0 register and counter are initialized to 0. this sets the prescaler to cko/2*, turns off the reload feature, disables timer counting, and initializes the timer to its inactive state. the act of reset- ting the chip does not cause a timer interrupt. note that the period register is not initialized on reset. the t0en bit of the timerc register enables the clock to the timer. when t0en is a 1, the timer counts down to- wards 0. when t0en is a 0, the timer holds its current count. * frequency of cko/2 is equivalent to either cki/2 for the pll by- passed or related to cki by the pll multiplying factors. see sec- tion 4.12, clock synthesis. the prescale field of the timerc register selects one of 16 possible clock rates for the timer input clock (see table 31, timerc register). setting the disable bit of the timerc register to a logic 1 shuts down the timer and the prescaler for power sav- ings. setting the timerdis, bit 4, in the powerc register has the same effect of shutting down the timer. the disable bit and the timerdis bit are cleared by writ- ing a 0 to their respective registers to restore the normal operating mode. 4.11 jtag test port the dsp1629 uses a jtag/ ieee 1149.1 standard five- wire test port (tdi, tdo, tck, tms, trst) for self-test and hardware emulation. an instruction register, a boundary-scan register, a bypass register, and a device identification register have been implemented. the de- vice identification register coding for the dsp1629 is shown in table 37. the instruction register (ir) is 4 bits long. the instruction for accessing the device id is 0xe (1110). the behavior of the instruction register is sum- marized in table 10. cell 0 is the lsb (closest to tdo). the first line shows the cells in the ir that capture from a parallel input in the capture-ir controller state. the second line shows the cells that always load a logic 1 in the capture-ir controller state. the third line shows the cells that always load a logic 0 in the capture-ir control- ler state. cell 3 (msb of ir) is tied to status signal pint, and cell 2 is tied to status signal jint. the state of these signals can therefore be captured during capture-ir and shifted out during shift-ir controller states. boundary-scan register all of the chip's inputs and outputs are incorporated in a jtag scan path shown in table 11. the types of boundary-scan cells are as follows: n i = input cell n o = 3-state output cell n b = bidirectional (i/o) cell n oe = 3-state control cell n dc = bidirectional control cell table 10. jtag instruction register ir cell #: 3 2 1 0 parallel input? y y n n always logic 1? n n n y always logic 0? n n y n
data sheet dsp1629 digital signal processor march 2000 26 lucent technologies inc. 4 hardware architecture (continued) note that the direction of shifting is from tdi to cell 104 to cell 103 . . . to cell 0 of tdo. * please refer to pin multiplexing in section 4.1 for a description of pin multiplexing of bio, phif, vec[3:0], and sio2. ? note that shifting a zero into this cell in the mode to scan a zero into the chip will disable the processor clocks just as th e stop pin will. ? when the jtag sample instruction is used, this cell will have a logic one regardless of the state of the pin. table 11. jtag boundary-scan register cell type signal name/function cell type signal name/function 0 oe controls cells 1, 2731 69 b ock2/pcsn * 1 o cko 70 dc controls cell 71 2irstb 71bdo2/pstat* 3 dc controls cell 4 72 dc controls cell 73 4 b trap 73 b sync2/pbsel* 5i stop ? 74 dc controls cell 75 6 o iack 75 b ild2/pids* 7 i int0 76 dc controls cell 77 8 oe controls cells 6, 1025, 49, 50, 78, 79 77 b old2/pods* 9 i int1 78 o ibf2/pibf* 1025 o ab[0:15] 79 o obe2/pobe* 26 i exm 80 dc controls cell 81 27 o rwn 81 b ick2/pb0* 2831 o erom, eramlo, eramhi, io 82 dc controls cell 83 3236 b db[0:4] 83 b di2/pb1* 37 dc controls cells 3236, 3848 84 dc controls cell 85 3848 b db[5:15] 85 b doen2/pb2* 49 o obe1 86 dc controls cell 87 50 o ibf1 87 b sadd2/pb3* 51 i di1 88 dc controls cell 89 52 dc controls cell 53 89 b iobit0/pb4* 53 b ild1 90 dc controls cell 91 54 dc controls cell 55 91 b iobit1/pb5* 55 b ick1 92 dc controls cell 93 56 dc controls cell 57 93 b iobit2/pb6* 57 b ock1 94 dc controls cell 95 58 dc controls cell 59 95 b iobit3/pb7* 59 b old1 96 dc controls cell 97 60 oe controls cell 61 97 b vec3/iobit4* 61 o do1 98 dc controls cell 99 62 dc controls cell 63 99 b vec2/iobit5* 63 b sync1 100 dc controls cell 101 64 dc controls cell 65 101 b vec1/iobit6* 65 b sadd1 102 dc controls cell 103 66 dc controls cell 67 103 b vec0/iobit7* 67 b doen1 104 i cki ? 68 dc controls cell 69
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 27 4 hardware architecture (continued) 4.12 clock synthesis figure 7. clock source block diagram powerc ring oscillator m u x 2 n phase detector charge pump vco vco clock f vco loop filter m lf[3:0] mbits[4:0] nbits[2:0] pll/synthesizer cki input clock lock (flag to indicate lock condition of pll) f cki f slow clock slowcki pllc pllen internal processor clock f internal clock pllsel f cki 5-4520 (f) the dsp1629 provides an on-chip, programmable clock synthesizer. figure 7 is the clock source diagram. the 1x cki input clock, the output of the synthesizer, or a slow internal ring oscillator can be used as the source for the internal dsp clock. the clock synthesizer is based on a phase-locked loop (pll), and the terms clock synthesizer and pll are used interchangeably. on powerup, cki is used as the clock source for the dsp. this clock is used to generate the internal proces- sor clocks and cko, where f cki = f cko . setting the ap- propriate bits in the pllc control register (described in table 32) will enable the clock synthesizer to become the clock source. the powerc register, which is dis- cussed in section 4.13, can override the selection to stop clocks or force the use of the slow clock for low- power operation. pll control signals the input to the pll comes from one of the three mask- programmable clock options: cmos, or small-signal. the pll cannot operate without an external input clock. to use the pll, the pll must first be allowed to stabi- lize and lock to the programmed frequency. after the pll has locked, the lock flag is set and the lock detect circuitry is disabled. the synthesizer can then be used as the clock source. setting the pllsel bit in the pllc register will switch sources from f cki to f vco /2 without glitching. it is important to note that the setting of the pllc register must be maintained. otherwise, the pll will seek the new set point. every time the pllc register is written, the lock flag is reset.
data sheet dsp1629 digital signal processor march 2000 28 lucent technologies inc. 4 hardware architecture (continued) the frequency of the pll output clock, f vco , is deter- mined by the values loaded into the 3-bit n divider and the 5-bit m divider. when the pll is selected and locked, the frequency of the internal processor clock is related to the frequency of cki by the following equa- tions: f vco = f cki * m/n f internal clock = f cko = f vco ? ? ? ? 2 the frequency of the vco, f vco , must fall within the range listed in table 63. also note that f vco must be at least twice f cki . the coding of the mbits and nbits is described as fol- lows: mbits = m - - - - 2 if (n = 1) nbits = 0x7 else nbits = n - - - - 2 where n ranges from 1 to 8 and m ranges from 2 to 20. the loop filter bits lf[3:0] should be programmed ac- cording to table 64. two other bits in the pllc register control the pll. clear- ing the pllen bit powers down the pll; setting this bit powers up the pll. clearing the pllsel bit deselects the pll so that the dsp is clocked by a 1x version of the cki input; setting the pllsel bit selects the pll- generated clock for the source of the dsp internal pro- cessor clock. the pllc register is cleared on reset and powerup. therefore, the dsp comes out of reset with the pll deselected and powered down. m and n should be changed only while the pll is deselected. the val- ues of m and n should not be changed when powering down or deselecting the pll. as previously mentioned, the pll also provides a user flag, lock, to indicate when the loop has locked. when this flag is not asserted, the pll output is unstable. the dsp should not be switched to the pll-based clock without first checking that the lock flag is set. the lock flag is cleared by writing to the pllc register. when the pll is deselected, it is necessary to wait for the pll to relock before the dsp can be switched to the pll- based clock. before the input clock is stopped, the pll should be powered down. otherwise, the lock flag will not be reset and there may be no way to determine if the pll is stable, once the input clock is applied again. the lock-in time depends on the frequency of operation and the values programmed for m and n (see table 64).
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 29 4 hardware architecture (continued) pll programming examples the following section of code illustrates how the pll would be initialized on powerup, assuming the following oper- ating conditions: n cki input frequency = 10 mhz n internal clock and cko frequency = 50 mhz n vco frequency = 100 mhz n input divide down count n = 2 (set nbits[2:0] = 000 to get n = 2, as described in table 32.) n feedback down count m = 20 (set mbits[4:0] = 10010 to get m = 18 + 2 = 20, as described in table 32.) the device would come out of reset with the pll disabled and deselected. pllinit: pllc = 0x2912 /* running cki input clock at 10 mhz, set up counters in pll */ pllc = 0xa912 /* power on pll, but pll remains deselected */ call pllwait /* loop to check for lock flag assertion */ pllc = 0xe912 /* select high-speed, pll clock */ goto start /* user's code, now running at 50 mhz */ pllwait: if lock return goto pllwait programming examples which illustrate how to use the pll with the various power management modes are listed in section 4.13. latency the switch between the cki-based clock and the pll-based clock is synchronous. this method results in the actual switch taking place several cycles after the pllsel bit is changed. during this time, actual code can be executed, but it will be at the previous clock rate. table 12 shows the latency times for switching between cki-based and pll- based clocks. in the example given, the delay to switch to the pll source is 14 cko cycles and to switch back is 1131 cko cycles. frequency accuracy and jitter when using the pll to multiply the input clock frequency up to the instruction clock rate, it is important to realize that although the average frequency of the internal clock and cko will have about the same relative accuracy as the input clock, noise sources within the dsp will produce jitter on the pll clock such that each individual clock period will have some error associated with it. the pll is guaranteed only to have sufficiently low jitter to operate the dsp, and thus, this clock should not be used as an input to jitter-sensitive devices in the system. v dda and v ssa connections the pll has its own power and ground pins, v dda and v ssa . additional filtering should be provided for v dda in the form of a ferrite bead connected from v dda to v dd and two decoupling capacitors (4.7 m f tantalum in parallel with a 0.01 m f ceramic) from v dda to v ss . v ssa can be connected directly to the main ground plane. this recommen- dation is subject to change and may need to be modified for specific applications depending on the characteristics of the supply noise. note: for devices with the cmos clock input option, the cki2 pin should be connected to v ssa . table 12. latency times for switching between cki and pll-based clocks minimum latency (cycles) maximum latency (cycles) switch to pll-based clock 1n + 2 switch from pll-based clock m/n + 1 m + m/n + 1
data sheet dsp1629 digital signal processor march 2000 30 lucent technologies inc. 4 hardware architecture (continued) 4.13 power management there are three different control mechanisms for putting the dsp1629 into low-power modes: the powerc control register, the stop pin, and the await bit in the alf reg- ister. the pll can also be disabled with the pllen bit of the pllc register for more power saving. powerc control register bits the powerc register has 10 bits that power down vari- ous portions of the chip and select the clock source: xtloff: assertion of the xtloff bit powers down the small-signal input circuit, disabling the internal proces- sor clock. since the small-signal input circuit takes many cycles to stabilize, care must be taken with the turn-on sequence, as described later. slowcki: assertion of the slowcki bit selects the ring oscillator as the clock source for the internal pro- cessor clock instead of cki or the pll. when cki or the pll is selected, the ring oscillator is powered down. switching of the clocks is synchronized so that no par- tial or short clock pulses occur. two nops should follow the instruction that sets or clears slowcki. nock: assertion of the nock bit synchronously turns off the internal processor clock, regardless of whether its source is provided by cki, the pll, or the ring oscil- lator. the nock bit can be cleared by resetting the chip with the rstb pin, or asserting the int0 or int1 pins. two nops should follow the instruction that sets nock. the pll remains running, if enabled, while nock is set. int0en: this bit allows the int0 pin to asynchronously clear the nock bit, thereby allowing the device to con- tinue program execution from where it left off without any loss of state. no chip reset is required. it is recom- mended that, when int0en is to be used, the int0 interrupt be disabled in the inc register so that an unin- tended interrupt does not occur. after the program re- sumes, the int0 interrupt in the ins register should be cleared. int1en: this bit enables the int1 pin to be used as the nock clear, exactly like int0en previously described. the following control bits power down the peripheral i/o units of the dsp. these bits can be used to further reduce the power consumption during standard sleep mode. sio1dis: this is a powerdown signal to the sio1 i/o unit. it disables the clock input to the unit, thus eliminat- ing any sleep power associated with the sio1. since the gating of the clocks may result in incomplete trans- actions, it is recommended that this option be used in applications where the sio1 is not used or when reset may be used to reenable the sio1 unit. otherwise, the first transaction after reenabling the unit may be corrupt- ed. sio2dis: this bit powers down the sio2 in the same way sio1dis powers down the sio1. phifdis: this is a powerdown signal to the parallel host interface. it disables the clock input to the unit, thus eliminating any sleep power associated with the phif. since the gating of the clocks may result in incomplete transactions, it is recommended that this option be used in applications where the phif is not used, or when re- set may be used to reenable the phif. otherwise, the first transaction after reenabling the unit may be corrupt- ed. timerdis: this is a timer disable signal which disables the clock input to the timer unit. its function is identical to the disable field of the timerc control register. writ- ing a 0 to the timerdis field will continue the timer op- eration. figure 8 shows a functional view of the effect of the bits of the powerc register on the clock circuitry. it shows only the high-level operation of each bit. not shown are the bits that power down the peripheral units. stop pin assertion (active-low) of the stop pin has the same ef- fect as setting the nock bit in the powerc register. the internal processor clock is synchronously disabled until the stop pin is returned high. once the stop pin is re- turned high, program execution will continue from where it left off without any loss of state. no chip reset is required. the pll remains running, if enabled, during stop assertion. the pllc register bits the pllen bit of the pllc register can be used to power down the clock synthesizer circuitry. before shutting down the clock synthesizer circuitry, the system clock should be switched to either cki using the pllsel bit of pllc, or to the ring oscillator using the slowcki bit of powerc.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 31 4 hardware architecture (continued) notes: the functions in the shaded ovals are bits in the powerc control register. the functions in the nonshaded ovals are bits in the pllc control register. deep sleep is the state arrived at either by a hardware or software stop of the internal processor clock. the switching of the multiplexers and the synchronous gate is designed so that no partial clocks or glitching will occur. when the deep sleep state is entered with the ring oscillator selected, the internal processor clock is turned off before the r ing oscillator is pow- ered down. pll select is the pllsel bit of pllc ; pll powerdown is the pllen bit of pllc . figure 8. power management using the powerc and the pllc registers cki2 small signal clock ring oscillator stop xtloff mask-programmable option off cki rstb cmos input clock sync. gate slowcki sync. mux internal processor clock clear nock disable int0 int0en on int1 int1en deep sleep hw stop sw stop nock pllen pllsel pll f vco/2 f slow clock f internal clock f cki deep sleep 5-4124 (f).h
data sheet dsp1629 digital signal processor march 2000 32 lucent technologies inc. 4 hardware architecture (continued) await bit of the alf register setting the await bit of the alf register causes the pro- cessor to go into the standard sleep state or power-sav- ing standby mode. operation of the await bit is the same as in the dsp1610, dsp1611, dsp1616, dsp1617, and dsp1618. in this mode, the minimum circuitry required to process an incoming interrupt re- mains active, and the pll remains active if enabled. an interrupt will return the processor to the previous state, and program execution will continue. the action result- ing from setting the await bit and the action resulting from setting bits in the powerc register are mostly inde- pendent. as long as the processor is receiving a clock, whether slow or fast, the dsp may be put into standard sleep mode with the await bit. once the await bit is set, the stop pin can be used to stop and later restart the processor clock, returning to the standard sleep state. if the processor clock is not running, however, the await bit cannot be set. power management sequencing there are important considerations for sequencing the power management modes. the small-signal clock in- put circuit has a start-up delay which must be taken into ac- count, and the pll requires a delay to reach lock-in. al- so, the chip may or may not need to be reset following a return from a low-power state. devices with a small-signal input clocking option may use the xtloff bit in the powerc register to power down the on-chip oscillator or small-signal circuitry, thereby reducing the power dissipation. when reen- abling the oscillator or the small-signal circuitry, it is im- portant to bear in mind that a start-up interval exists during which time the clocks are not stable. two scenarios exist here: 1. immediate turn-off, turn-on with rstb: this sce- nario applies to situations where the target device is not required to execute any code while the small-sig- nal input circuit is powered down and where restart from a reset state can be tolerated. in this case, the processor clock derived from either the oscillator or the small-signal input is running when xtloff is as- serted. this effectively stops the internal processor clock. when the system chooses to reenable the os- cillator or small-signal input, a reset of the device will be required. the reset pulse must be of sufficient du- ration for the small-signal start-up interval to be sat- isfied (required for the small-signal input circuit to reach its dc operating point). a minimum reset pulse of 20 s will be adequate. the falling edge of the re- set signal, rstb, will asynchronously clear the xtloff field, thus reenabling the power to the small-signal circuitry. the target dsp will then start execution from a reset state, following the rising edge of rstb. 2. running from slow clock while xtloff active: the second scenario applies to situations where the de- vice needs to continue execution of its target code. in this case, the device switches to the slow ring os- cillator clock first, by enabling the slowcki field. then, if the small-signal input is being used, power down this circuitry by writing a 1 to the xtloff field. two nops are needed in between the two write oper- ations to the powerc register. the target device will then continue execution of its code at slow speed, while the small-signal input clock is turned off. switching from the slow clock back to the high-speed clock is then accomplished in three user steps. first, xtloff is cleared. then, a user-programmed rou- tine sets the internal timer to a delay to wait for the small-signal input oscillations to become stable. when the timer counts down to zero, the high-speed clock is selected by clearing the slowcki field, ei- ther in the timer's interrupt service routine or follow- ing a timer polling loop. if pll operation is desired, then an additional routine is necessary to enable the pll and wait for it to lock.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 33 4 hardware architecture (continued) power management examples without the pll the following examples show the more significant options for reducing the power dissipation. these are valid only if the pllc register is set to disable and deselect the pll (pllen = 0, pllsel = 0). standard sleep mode. this is the standard sleep mode. while the processor is clocked with a high-speed clock, cki, the alf register's await bit is set. peripheral units may be turned off to further reduce the sleep power. powerc = 0x00f0 /* turn off peripherals, core running with cki */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. only sleep power */ nop /* consumed here until.... interrupt wakes up the device */ cont: . . . /* user code executes here */ powerc = 0x0 /* turn peripheral units back on */ sleep with slow internal clock. in this case, the ring oscillator is selected to clock the processor before the device is put to sleep. this will reduce the power dissipation while waiting for an interrupt to continue program execution. powerc = 0x40f0 /* turn off peripherals and select slow clock */ 2*nop /* wait for it to take effect */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. reduced sleep power */ nop /* consumed here.... interrupt wakes up the device */ cont: . . . /* user code executes here */ powerc = 0x00f0 /* select high-speed clock */ 2*nop /* wait for it to take effect */ powerc = 0x0000 /* turn peripheral units back on */ note that, in this case, the wake-up latency is determined by the period of the ring oscillator clock. sleep with slow internal clock and small-signal disabled. if the target device contains the small-signal clock option, the clock input circuitry can be powered down to further reduce power. in this case, the slow clock must be selected first. powerc = 0x40f0 /* turn off peripherals and select slow clock */ 2*nop /* wait for it to take effect */ powerc = 0xc0f0 /* turn off the small-signal input buffer */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. reduced sleep power */ nop /* consumed here.... interrupt wakes up the device */ powerc = 0x40f0 /* clear xtloff, reenable small-signal */ call xtlwait /* wait until small-signal is stable */ cont: powerc = 0x00f0 /* select high-speed clock */ 2*nop /* wait for it to take effect */ powerc = 0x0000 /* turn peripheral units back on */ note that, in this case, the wake-up latency is dominated by the small-signal start-up period.
data sheet dsp1629 digital signal processor march 2000 34 lucent technologies inc. 4 hardware architecture (continued) software stop. in this case, all internal clocking is disabled. int0, int1, or rstb may be used to reenable the clocks.the power management must be done in correct sequence. powerc = 0x4000 /* slowcki asserted */ 2*nop /* wait for it to take effect */ powerc = 0xd000 /* xtloff asserted if applicable and int0en asserted */ inc = noint0 /* disable the int0 interrupt */ sopor:powerc = 0xf000 /* nock asserted, all clocks stop */ /* minimum switching power consumed here */ 3*nop /* some nops will be needed */ /* int0 pin clears the nock field, clocking resumes */ cont: powerc = 0x4000 /* int0en cleared and xtloff cleared, if applicable*/ call waitxtl /* wait for the small-signal to */ /* stabilize, if applicable*/ powerc = 0x0 /* clear slowcki field, back to high speed */ 2*nop /* wait for it to take effect */ ins = 0x0010 /* clear the int0 status bit */ in this case also, the wake-up latency is dominated by the small-signal start-up period. the previous examples do not provide an exhaustive list of options available to the user. many different clocking possibilities exist for which the target device may be programmed, depending on: n the clock source to the processor. n whether the user chooses to power down the peripheral units. n the operational state of the small-signal clock input, powered or unpowered. n whether the internal processor clock is disabled through hardware or software. n the combination of power management modes the user chooses. n whether or not the pll is enabled. an example subroutine for xtlwait follows: xtlwait: timer0 = 0x2710 /* load a count of 10,000 into the timer */ timerc = 0x0010 /* start the timer with a prescale of two */ inc = 0x0000 /* disable the interrupts */ loop1: a0 = ins /* poll the ins register */ a0 = a0 & 0x0100 /* check bit 8 (time) of the ins register */ if eq goto loop1 /* loop if the bit is not set */ ins = 0x0100 /* clear the time interrupt bit */ return /* return to the main program */
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 35 4 hardware architecture (continued) power management examples with the pll the following examples show the more significant options for reducing power dissipation if operation with the pll clock synthesizer is desired. standard sleep mode, pll running. this mode would be entered in the same manner as without the pll. while the input to the clock synthesizer, cki, remains running, the alf register's await bit is set. the pll will continue to run and dissipate power. peripheral units may be turned off to further reduce the sleep power. powerc = 0x00f0 /* turn off peripherals, core running with pll */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. only sleep power plus pll */ nop /* power consumed here.... interrupt wakes up the device */ cont: . . . /* user code executes here */ powerc = 0x0 /* turn peripheral units back on */ sleep with slow internal clock, pll running. in this case, the ring oscillator is selected to clock the processor before the device is put to sleep. this will reduce power dissipation while waiting for an interrupt to continue program execution. powerc = 0x40f0 /* turn off peripherals and select slow clock */ 2*nop /* wait for slow clock to take effect */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. reduced sleep power, pll */ nop /* power, and ring oscillator power consumed here... */ /* interrupt wakes up the device */ cont: . . . /* user code executes here */ powerc = 0x00f0 /* select high-speed pll based clock */ 2*nop /* wait for it to take effect */ powerc = 0x0000 /* turn peripheral units back on */
data sheet dsp1629 digital signal processor march 2000 36 lucent technologies inc. 4 hardware architecture (continued) sleep with slow internal clock and small-signal disabled, pll disabled. if the target device contains the small- signal clock option, the clock input circuitry can be powered down to further reduce power. in this case, the slow clock must be selected first, and then the pll must be disabled, since the pll cannot run without the clock input circuitry being active. powerc = 0x40f0 /* turn off peripherals and select slow clock */ 2*nop /* wait for slow clock to take effect */ pllc = 0x29f2 /* disable pll (assume n = 1,m = 20, lf = 1001) */ powerc = 0xc0f0 /* disable small-signal input buffer */ sleep:a0 = 0x8000 /* set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* stop internal processor clock, interrupt circuits */ nop /* active */ } nop /* needed for bedtime execution. reduced sleep power nop /* consumed here.... interrupt wakes up device */ powerc = 0x40f0 /* clear xtloff, leave pll disabled */ call xtlwait /* wait until small-signal is stable */ pllc = 0xe9f2 /* enable pll, continue to run off slow clock */ call pllwait /* loop to check for lock flag assertion */ cont: powerc = 0x00f0 /* select high-speed pll based clock */ 2*nop /* wait for it to take effect */ powerc = 0x0000 /* turn peripherals back on */ software stop, pll disabled. in this case, all internal clocking is disabled. int0, int1, or rstb may be used to reenable the clocks. the power management must be done in the correct sequence, with the pll being disabled before shutting down the clock input buffer. powerc = 0x4000 /* slowcki asserted */ 2*nop /* wait for slow clock to take effect */ pllc = 0x29f2 /* disable pll (assume n = 1, m = 20, lf = 1001) */ powerc = 0xd000 /* xtloff asserted, if applicable and int0en /* asserted */ sopor:powerc = 0xf000 /* nock asserted, all clocks stop */ /* minimum switching power consumed here */ 3*nop /* some nops will be needed */ /* int0 pin clears nock field, clocking resumes */ cont: powerc = 0x4000 /* intoen cleared and xtloff cleared, if applicable */ call xtlwait /* wait until small-signal is stable */ /* if applicable */ pllc = 0xe9f2 /* enable pll, continue to run off slow clock */ call pllwait /* loop to check for lock flag assertion */ powerc = 0x0 /* select high-speed pll based clock */ 2*nop /* wait for it to take effect */ ins = 0x0010 / * clear the int0 status bit */
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 37 5 software architecture 5.1 instruction set the dsp1629 processor has seven types of instruc- tions: multiply/alu, special function, control, f3 alu, bmu, cache, and data move. the multiply/alu instruc- tions are the primary instructions used to implement sig- nal processing algorithms. statements from this group can be combined to generate multiply/accumulate, log- ical, and other alu functions and to transfer data be- tween memory and registers in the data arithmetic unit. the special function instructions can be conditionally executed based on flags from the previous alu or bmu operation, the condition of one of the counters, or the value of a pseudorandom bit in the dsp1629 device. special function instructions perform shift, round, and complement functions. the f3 alu instructions enrich the operations available on accumulators. the bmu in- structions provide high-performance bit manipulation. the control instructions implement the goto and call commands. control instructions can also be executed conditionally. cache instructions are used to implement low-overhead loops, conserve program memory, and decrease the execution time of certain multiply/alu in- structions. data move instructions are used to transfer data between memory and registers or between accu- mulators and registers. see the dsp1611/17/18/27 digital signal processor information manual for a de- tailed description of the instruction set. the following operators are used in describing the in- struction set: n * 16 x 16-bit C> 32-bit multiplication or register- indirect addressing when used as a prefix to an address register or denotes direct addressing when used as a prefix to an immediate n + 36-bit addition ? n C 36-bit subtraction ? n >> arithmetic right shift n >>> logical right shift n << arithmetic left shift n <<< logical left shift n | 36-bit bitwise or ? n & 36-bit bitwise and ? n ^ 36-bit bitwise exclusive or ? n : compound address swapping, accumulator shuffling n ~ one's complement ? these are 36-bit operations. one operand is 36-bit data in an ac- cumulator; the other operand may be 16, 32, or 36 bits. multiply/alu instructions note that the function statements and transfer state- ments in table 13 are chosen independently. any func- tion statement (f1) can be combined with any transfer statement to form a valid multiply/alu instruction. if ei- ther statement is not required, a single statement from either column also constitutes a valid instruction. the number of cycles to execute the instruction is a function of the transfer column. (an instruction with no transfer statement executes in one instruction cycle.) whenever pc, pt, or rm is used in the instruction and points to ex- ternal memory, the programmed number of wait-states must be added to the instruction cycle count. all multi- ply/alu instructions require one word of program mem- ory. the no-operation (nop) instruction is a special-case encoding of a multiply/alu instruction and executes in one cycle. the assembly-language representation of a nop is either nop or a single semicolon. a single-cycle squaring function is provided in dsp1629. by setting the x = y = bit in the auc register, any instruction that loads the high half of the y register also loads the x register with the same value. a subse- quent instruction to multiply the x register and y register results in the square of the value being placed in the p register. the instruction a0 = p p = x*y y = *r0++ with the x = y = bit set to one will read the value pointed to by r0, load it to both x and y, multiply the previously fetched value of x and y, and transfer the previous prod- uct to a0. a table of values pointed to by r0 can thus be squared in a pipeline with one instruction cycle per each value. multiply/alu instructions that use x = x transfer statements (such as a0 = p p = x*y y = *r0++ x = *pt++) are not recommended for squaring because pt will be incremented even though x is not loaded from the value pointed to by pt. also, the same conflict wait occurrenc- es from reading the same bank of internal memory or reading from external memory apply, since the x space fetch occurs (even though its value is not used).
data sheet dsp1629 digital signal processor march 2000 38 lucent technologies inc. 5 software architecture (continued) ? the l in [ ] is an optional argument that specifies the low 16 bits of at or y . ? add cycles for: 1. when an external memory access is made in x or y space and wait-states are programmed, add the number of wait-states. 2. if an x space access and a y space access are made to the same bank of dpram in one instruction, add one cycle. note: for transfer statements when loading the upper half of an accumulator, the lower half is cleared if the corre- sponding clr bit in the auc register is zero. auc is cleared by reset. table 13. multiply/alu instructions function statement transfer statement ? cycles (out/in cache) ? p = x * y y = y x = x 2/1 ad = p p = x * y y = at x = x 2/1 ad = as + p p = x * y y[l] = y 1/1 ad = as C p p = x * y at[l] = y 1/1 ad = p x = y 1/1 ad = as + p y 1/1 ad = as C p y = y[l] 2/2 ad = y y = at[l] 2/2 ad = as + y z:y x = x 2/2 ad = as C y z:y[l] 2/2 ad = as & y z:at[l] 2/2 ad = as | y ad = as ^ y as C y as & y table 14. replacement table for multiply/alu instructions replace value meaning ad, as, at a0, a1 one of two dau accumulators. x *pt++, *pt++i x memory space location pointed to by pt. pt is postmodified by +1 and i, respectively. y *rm, *rm++, *rm--, rm++j ram location pointed to by rm (m = 0, 1, 2, 3). rm is postmodified by 0, +1, C1, or j, respectively. z *rmzp, *rmpz, *rmm2, *rmjk read/write compound addressing. rm (m = 0, 1, 2, 3) is used twice. first, postmodified by 0, +1, C1, or j, respectively; and, second, post- modified by +1, 0, +2, or k, respectively.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 39 5 software architecture (continued) special function instructions all forms of the special function require one word of program memory and execute in one instruction cycle. (if pc points to external memory, add programmed wait-states.) ad = as load destination accumulator from source accumulator ad = Cas 2's complement ad = ~as* 1's complement ad = rnd(as) round upper 20 bits of accumulator adh = ash + 1 increment upper half of accumulator (lower half cleared) ad = as + 1 increment accumulator ad = y load accumulator with 32-bit y register value with sign extend ad = p load accumulator with 32-bit p register value with sign extend the above special functions can be conditionally executed, as in: if con instruction and with an event counter ifc con instruction which means: if con is true then c1 = c1 + 1 instruction c2 = c1 else c1 = c1 + 1 the above special function statements can be executed unconditionally by writing them directly, e.g., a0 = a1. * this function is not available for the dsp16a. ad = as >> 1 ad = as >> 4 ad = as >> 8 ad = as >> 16 } arithmetic right shift (sign preserved) of 36-bit accumulators ad = as << 1 ad = as << 4 ad = as << 8 ad = as << 16 } arithmetic left shift (sign not preserved) of the lower 32 bits of accumulators (upper 4 bits are sign-bit-extended from bit 31 at the completion of the shift) table 15. replacement table for special function instructions replace value meaning ad as a0, a1 one of two dau accumulators. con mi, pl, eq, ne, gt, le, lvs, lvc, mvs, mvc, c0ge, c0lt, c1ge, c1lt, heads, tails, true, false, allt, allf, somet, somef, oddp, evenp, mns1, nmns1, npint, njint, lock see table 17 for definitions of mnemonics.
data sheet dsp1629 digital signal processor march 2000 40 lucent technologies inc. 5 software architecture (continued) control instructions all control instructions executed unconditionally execute in two cycles, except icall which takes three cycles. control instructions executed conditionally execute in three instruction cycles. (if pc, pt, or pr point to external memory, add programmed wait-states.) control instructions executed unconditionally require one word of program memory, while control instructions executed conditionally require two words. control instructions cannot be executed from the cache. goto ja ? goto pt call ja ? call pt icall ? return (goto pr) ireturn (goto pi) ?the goto ja and call ja instructions should not be placed in the last or next-to-last instruction before the boundary of a 4 kwords page. if the goto or call is placed there, the program counter will have incremented to the next page and the jump will be to the next page, rather than to the desired current page. ?the icall instruction is reserved for development system use. the above control instructions, with the exception of ireturn and icall, can be conditionally executed. for example: if le goto 0x0345 table 16. replacement table for control instructions replace value meaning con mi, pl, eq, ne, gt, le, nlvs, lvc, mvs, mvc, c0ge, c0lt, c1ge, c1lt, heads, tails, true, false, allt, allf, somet, somef, oddp, evenp, mns1, nmns1, npint, njint, lock see table 17 for definitions of mnemonics. ja 12-bit value least significant 12 bits of absolute address within the same 4 kwords memory section.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 41 5 software architecture (continued) conditional mnemonics (flags) table 17 lists mnemonics used in conditional execution of special function and control instructions. notes: testing the state of the counters (c0 or c1) automatically increments the counter by one. the heads or tails condition is determined by a randomly set or cleared bit, respectively. the bit is randomly set with a proba bility of 0.5. a random rounding function can be implemented with either heads or tails. the random bit is generated by a ten-stage pseudorandom sequen ce generator (psg) that is updated after either a heads or tails test. the pseudorandom sequence may be reset by writing any value to the pi register, except during an interrupt service routine (isr). while in an isr, writing to the pi register updates the register and does not reset the psg. if not in an isr, writing to the pi register resets the psg. (the pi register is updated, but will be written with the contents of the pc on the next instruction.) interrupts must be disabled when writing to the pi register. if an interrupt is taken after the pi write, but before pi is upda ted with the pc value, the ireturn instruction will not return to the correct location. if the rand bit in the auc register is set, however, writing t he pi register never resets the psg. table 17. dsp1629 conditional mnemonics test meaning test meaning pl result is nonnegative (sign bit is bit 35). 3 0 mi result is negative. < 0 eq result is equal to 0. = 0 ne result is not equal to 0. 1 0 gt result is greater than 0. > 0 le result is less than or equal to 0. 0 lvs logical overflow set. * * result is not representable in the 36-bit accumulators (36-bit overflow). lvc logical overflow clear. mvs mathematical overflow set. ? ? bits 3531 are not the same (32-bit overflow). mvc mathematical overflow clear. c0ge counter 0 greater than or equal to 0. c0lt counter 0 less than 0. c1ge counter 1 greater than or equal to 0. c1lt counter 1 less than 0. heads pseudorandom sequence bit set. tails pseudorandom sequence bit clear. true the condition is always satisfied in an if in- struction. false the condition is never satisfied in an if instruc- tion. allt all true, all bio input bits tested compared successfully. allf all false, no bio input bits tested compared successfully. somet some true, some bio input bits tested com- pared successfully. somef some false, some bio input bits tested did not compare successfully. oddp odd parity, from bmu operation. evenp even parity, from bmu operation. mns1 minus 1, result of bmu operation. nmns1 not minus 1, result of bmu operation. npint not pint, used by hardware development system. njint not jint, used by hardware development system. lock the pll has achieved lock and is stable.
data sheet dsp1629 digital signal processor march 2000 42 lucent technologies inc. 5 software architecture (continued) f3 alu instructions these instructions are implemented in the dsp1600 core. they allow accumulator two-operand operations with ei- ther another accumulator, the p register, or a 16-bit immediate operand (im16). the result is placed in a destination accumulator that can be independently specified. all operations are done with the full 36 bits. for the accumulator with accumulator operations, both inputs are 36 bits. for the accumulator with p register operations, the p register is sign-extended into bits 3532 before the operation. for the accumulator high with immediate operations, the im- mediate is sign-extended into bits 3532 and the lower bits 150 are filled with zeros, except for the and opera- tion, for which they are filled with ones. these conventions allow the user to do operations with 32-bit immediates by programming two consecutive 16-bit immediate operations. the f3 alu instructions are shown in table 18. note: the f3 alu instructions that do not have a destination accumulator are used to set flags for conditional operations, i.e., bit test operations. f4 bmu instructions the bit manipulation unit in the dsp1629 provides a set of efficient bit manipulation operations on accumulators. it contains four auxiliary registers, ar<03> (arm, m = 0, 1, 2, 3), two alternate accumulators (aa0aa1), which can be shuffled with the working set, and four flags (oddp, evenp, mns1, and nmns1). the flags are testable by condi- tional instructions and can be read and written via bits 47 of the alf register. the bmu also sets the lmi, leq, llv, and lmv flags in the psw register. lmi = 1 if negative (i.e., bit 35 = 1) leq = 1 if zero (i.e., bits 350 are 0) llv = 1 if (a) 36-bit overflow, or if (b) illegal shift on field width/offset condition lmv = 1 if bits 3135 are not the same (32-bit overflow) the bmu instructions and cycle times follow. (if pc points to external memory, add programmed wait-states.) all bmu instructions require 1 word of program memory unless otherwise noted. please refer to the dsp1611/17/18/ 27 digital signal processor information manual for further discussion of the bmu instructions. table 18. f3 alu instructions f3 alu instructions * * if pc points to external memory, add programmed wait-states. cachable (one-cycle) not cachable (two-cycle) ? ?the h and l are required notation in these instructions. ad = as + at ad = as C at ad = as & at ad = as | at ad = as ^ at as C at as & at ad = as + p ad = as C p ad = as & p ad = as | p ad = as ^ p as C p as & p ad = ash + im16 ad = ash C im16 ad = ash & im16 ad = ash | im16 ad = ash ^ im16 ash C im16 ash & im16 ad = asl + im16 ad = asl C im16 ad = asl & im16 ad = asl | im16 ad = asl ^ im16 asl C im16 asl & im16
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 43 5 software architecture (continued) n barrel shifter: ad = as >> im16 arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle, 2-word. ad = as >> arm arithmetic right shift by arm (36-bit, sign filled in); 1-cycle. ad = as >> as arithmetic right shift by as (36-bit, sign filled in); 2-cycle. ad = as >>> im16 logical right shift by immediate (32-bit shift, 0s filled in); 2-cycle, 2-word. ad = as >>> arm logical right shift by arm (32-bit shift, 0s filled in); 1-cycle. ad = as >>> as logical right shift by as (32-bit shift, 0s filled in); 2-cycle. ad = as << im16 arithmetic left shift ? by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word. ad = as << arm arithmetic left shift ? by arm (36-bit shift, 0s filled in); 1-cycle. ad = as << as arithmetic left shift ? by as (36-bit shift, 0s filled in); 2-cycle. ad = as <<< im16 logical left shift by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word. ad = as <<< arm logical left shift by arm (36-bit shift, 0s filled in); 1-cycle. ad = as <<< as logical left shift by as (36-bit shift, 0s filled in); 2-cycle. ? not the same as the special function arithmetic left shift. here, the guard bits in the destination accumulator are shifted in to, not sign-extended. n normalization and exponent computation: ad = exp(as) detect the number of redundant sign bits in accumulator; 1-cycle. ad = norm(as, arm) normalize as with respect to bit 31, with exponent in arm ; 1-cycle. n bit field extraction and insertion: ad = extracts(as, im16) extraction with sign extension, field specified as immediate; 2-cycle, 2-word. ad = extracts(as, arm) extraction with sign extension, field specified in arm ; 1-cycle. ad = extractz(as, im16) extraction with zero extension, field specified as immediate; 2-cycle, 2-word. ad = extractz(as, arm) extraction with zero extension, field specified in arm ; 1-cycle. ad = insert(as, im16) bit field insertion, field specified as immediate; 2-cycle, 2-word. ad = insert(as, arm) bit field insertion, field specified in arm ; 2-cycle. note: the bit field to be inserted or extracted is specified as follows. the width (in bits) of the field is the upper byte of the operand (immediate or arm), and the offset from the lsb is in the lower byte. n alternate accumulator set: ad = as:aa0 shuffle accumulators with alternate accumulator 0 ( aa0 ); 1-cycle. ad = as:aa1 shuffle accumulators with alternate accumulator 1 ( aa1 ); 1-cycle. note: the alternate accumulator gets what was in as. ad gets what was in the alternate accumulator. table 19. replacement table for f3 alu instructions and f4 bmu instructions replace value meaning ad, at, as a0 or a1 one of the two accumulators. im16 immediate 16-bit data, sign-, zero-, or one-extended as appropriate. arm ar<03> one of the auxiliary bmu registers.
data sheet dsp1629 digital signal processor march 2000 44 lucent technologies inc. 5 software architecture (continued) cache instructions cache instructions require one word of program memory. the do instruction executes in one instruction cycle, and the redo instruction executes in two instruction cycles. (if pc points to external memory, add programmed wait- states.) control instructions and long immediate values cannot be stored inside the cache. the instruction formats are as follows: n do k { n instr1 n instr2 n . n . n . n instrn n } n redo k ? the assembly-language statement, do cloop (or redo cloop ), is used to specify that the number of iterations is to be taken from the cloop register. k is encoded as 0 in the instruction encoding to select cloop . when the cache is used to execute a block of instructions, the cycle timings of the instructions are as follows: 1. in the first pass, the instructions are fetched from program memory and the cycle times are the normal out-of- cache values, except for the last instruction in the block of n instructions. this instruction executes in two cycles. 2. during pass two through pass k C 1, each instruction is fetched from cache and the in-cache timings apply. 3. during the last (kth) pass, the block of instructions is fetched from cache and the in-cache timings apply, except that the timing of the last instruction is the same as if it were out-of-cache. 4. if any of the instructions access external memory, programmed wait-states must be added to the cycle counts. the redo instruction treats the instructions currently in the cache memory as another loop to be executed k times. using the redo instruction, instructions are reexecuted from the cache without reloading the cache. the number of iterations, k, for a do or redo can be set at run time by first moving the number of iterations into the cloop register (7 bits unsigned), and then issuing the do cloop or redo cloop . at the completion of the loop, the value of cloop is decremented to 0; hence, cloop needs to be written before each do cloop or redo cloop . table 20. replacement table for cache instructions replace instruction encoding meaning k cloop ? number of times the instructions are to be executed taken from bits 06 of the cloop register. 1 to 127 number of times the instructions to be executed is encoded in the instruction. n 1 to 15 1 to 15 instructions can be included.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 45 5 software architecture (continued) data move instructions data move instructions normally execute in two instruction cycles. (if pc or rm point to external memory, any pro- grammed wait-states must be added. in addition, if pc and rm point to the same bank of dpram, then one cycle must be added.) immediate data move instructions require two words of program memory; all other data move in- structions require only one word. the only exception to these statements is a special case immediate load (short immediate) instruction. if a yaau register is loaded with a 9-bit short immediate value, the instruction requires only one word of memory and executes in one instruction cycle. all data move instructions, except those doing long im- mediate loads, can be executed from within the cache. the data move instructions are as follows: n r = im16 n at[l] = r n sr = im9 n y = r n r = y n z : r n r = as[l] n dr = *(offset) n (offset) = dr notes: sioc, sioc2, tdms, tdms2, srta, and srta2 registers are not readable. when signed registers less than 16 bits wide (c0, c1, c2) are read, their contents are sign-extended to 16 bits. when unsigned registers less than 16 bits wide are read, their contents are zero-extended to 16 bits. loading an accumulator with a data move instruction does not affect the flags. table 21. replacement table for data move instructions replace value meaning r any of the registers in table 51 dr r<03>, a0[l], a1[l], y[l], p, pl, x, pt, pr, psw subset of registers accessible with direct addressing. as, at a0, a1 high half of accumulator. y * rm, * rm++, * rm--, * rm++j same as in multiply/alu instructions. z * rmzp, * rmpz, * rmm2, * rmjk same as in multiply/alu instructions. im16 16-bit value long immediate data. im9 9-bit value short immediate data for yaau registers. offset 5-bit value from instruction 11-bit value in base register value in bits [15:5] of ybase register form the 11 most significant bits of the base address. the 5-bit offset is concatenated to this to form a 16-bit address. sr r<03>, rb, re, j, k subset of registers for short immediate.
data sheet dsp1629 digital signal processor march 2000 46 lucent technologies inc. 5 software architecture (continued) 5.2 register settings tables 22 through 38 describe the programmable registers of the dsp1629 device. table 40 describes the register settings after reset. note that the following abbreviations are used in the tables: n x = don't care n r = read only n w = read/write the reserved (rsvd) bits in the tables should always be written with zeros to make the program compatible with future chip versions. table 22. serial i/o control registers * see tdms register, sync field. ? the bit definitions of the sioc2 register are identical to the sioc register bit definitions. sioc bit 109876543210 field dodly ld clk msb old ild ock ick olen ilen field value description dodly 0 1 do changes on the rising edge of ock. do changes on the falling edge of ock. this delay in driving do increases the hold time on do by half a cycle of ock. ld 0 1 in active mode, ild1 and/or old1 = ick1/16, active sync1 = ick1/[128/256*]. in active mode, ild1 and/or old1 = ock1/16, active sync1 = ock1/[128/256*]. clk 00 01 10 11 active clock = cki/2 (1x). active clock = cki/6 (1x). active clock = cki/8 (1x). active clock = cki/10 (1x). msb 0 1 lsb first. msb first. old 0 1 old1 is an input (passive mode). old1 is an output (active mode). ild 0 1 ild1 is an input (passive mode). ild1 is an output (active mode). ock 0 1 ock1 is an input (passive mode). ock1 is an output (active mode). ick 0 1 ick1 is an input (passive mode). ick1 is an output (active mode). olen 0 1 16-bit output. 8-bit output. ilen 0 1 16-bit input. 8-bit input. sioc2 ? bit 109876543210 field dodly2 ld2 clk2 msb2 old2 ild2 ock2 ick2 olen2 ilen2
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 47 5 software architecture (continued) table 23. time-division multiplex slot registers * see sioc register, ld field. ? select this mode when in multiprocessor mode. ?the tdms2 register bit definitions are identical to the tdms register bit definitions. tdms bit 9 8 7654321 0 field syncsp mode transmit slot sync field value description syncsp * * see sioc register, ld field. 0 ? 1 sync1 = ick1/128 if ld = 0*. sync1 = ock1/128 if ld = 1*. sync1 = ick1/256 if ld = 0*. sync1 = ock1/256 if ld = 1*. mode 0 multiprocessor mode off; doen1 is an input (passive mode). 1 multiprocessor mode on; doen1 is an output (active mode). transmit slot 1xxxxxx transmit slot 7. x1xxxxx transmit slot 6. xx1xxxx transmit slot 5. xxx1xxx transmit slot 4. xxxx1xx transmit slot 3. xxxxx1x transmit slot 2. xxxxxx1 transmit slot 1. sync 1 transmit slot 0, sync1 is an output (active mode). 0 sync1 is an input (passive mode). tdms2 ? bit 9 8 7654321 0 field syncsp2 * mode2 transmit slot2 sync2
data sheet dsp1629 digital signal processor march 2000 48 lucent technologies inc. 5 software architecture (continued) table 24. serial receive/transmit address registers table 25. multiprocessor protocol registers ?the saddx2 field definitions are identical to the saddx register field definitions. srta bit 1514131211109 876543210 field receive address transmit address field value description receive address 1xxxxxxx receive address 7. x1xxxxxx receive address 6. xx1xxxxx receive address 5. xxx1xxxx receive address 4. xxxx1xxx receive address 3. xxxxx1xx receive address 2. xxxxxx1x receive address 1. xxxxxxx1 receive address 0. transmit address 1xxxxxxx transmit address 7. x1xxxxxx transmit address 6. xx1xxxxx transmit address 5. xxx1xxxx transmit address 4. xxxx1xxx transmit address 3. xxxxx1xx transmit address 2. xxxxxx1x transmit address 1. xxxxxxx1 transmit address 0. srta2 * *the srta2 field definitions are identical to the srta register field definitions. bit 1514131211109 876543210 field receive address2 transmit address2 saddx bit field 158 70 write x write protocol field [7:0] read read protocol field [7:0] 0 saddx2 ? bit field 158 70 write x write protocol2 field [7:0] read read protocol2 field [7:0] 0
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 49 5 software architecture (continued) ?the auc is 9 bits [8:0]. the upper 7 bits [15:9] are always zero when read and should always be written with zeros to make the program compatible with future chip versions. the auc register is cleared at reset. table 26. processor status word (psw) register bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field dau flags x x a1[v] a1[35:32] a0[v] a0[35:32] field value description dau flags * * the dau flags can be set by either bmu or dau operations. wxxx lmilogical minus when set (bit 35 = 1). xwxx leqlogical equal when set (bit [35:0] = 0). xxwx llvlogical overflow when set. xxxw lmv mathematical overflow when set. a1[v] w accumulator 1 (a1) overflow when set. a1[35:32] wxxx accumulator 1 (a1) bit 35. xwxx accumulator 1 (a1) bit 34. xxwx accumulator 1 (a1) bit 33. xxxw accumulator 1 (a1) bit 32. a0[v] w accumulator 0 (a0) overflow when set. a0[35:32] wxxx accumulator 0 (a0) bit 35. xwxx accumulator 0 (a0) bit 34. xxwx accumulator 0 (a0) bit 33. xxxw accumulator 0 (a0) bit 32. table 27. arithmetic unit control (auc) register ? bit 8 7 6543210 field rand x=y= clr sat align field value description rand 0 1 pseudorandom sequence generator (psg) reset by writing the pi register only outside an interrupt service routine. psg never reset by writing the pi register. x=y= 0 1 normal operation. all instructions which load the high half of the y register also load the x register, allowing single-cycle squaring with p = x * y. clr 1xx clearing yl is disabled (enabled when 0). x1x clearing a1l is disabled (enabled when 0). xx1 clearing a0l is disabled (enabled when 0). sat 1x a1 saturation on overflow is disabled (enabled when 0). x1 a0 saturation on overflow is disabled (enabled when 0). align 00 a0, a1 ? ? ? ? p. 01 a0, a1 ? ? ? ? p/4. 10 a0, a1 ? ? ? ? p x 4 (and zeros written to the two lsbs). 11 a0, a1 ? ? ? ? p x 2 (and zero written to the lsb).
data sheet dsp1629 digital signal processor march 2000 50 lucent technologies inc. 5 software architecture (continued) * jint is a jtag interrupt and is controlled by the hds. it may be made unmaskable by the lucent technologies development system tools. encoding: a 0 disables an interrupt; a 1 enables an interrupt. encoding: a 0 indicates no interrupt. a 1 indicates an interrupt has been recognized and is pending or being ser- viced. if a 1 is written to bits 4, 5, or 8 of ins, the corresponding interrupt is cleared. table 28. parallel host interface control (phifc) register bit 157 6 5 4 3 2 1 0 field rsvd psobef pflagsel pflag pbself pstrb pstrobe pmode field value description pmode 0 1 8-bit data transfers. 16-bit data transfers. pstrobe 0 1 intel protocol: pids and pods data strobes. motorola protocol: prwn and pds data strobes. pstrb 0 1 when pstrobe = 1, pods pin (pds) active-low. when pstrobe = 1, pods pin (pds) active-high. pbself 0 1 in either mode, pbsel pin = 0 ? pdx0 low byte. see table 7. if pmode = 0, pbsel pin = 1 ? pdx0 low byte. if pmode = 1, pbsel pin = 0 ? pdx0 high byte. pflag 0 1 pibf and pobe pins active-high. pibf and pobe pins active-low. pflagsel 0 1 normal. pibf flag ored with pobe flag and output on pibf pin; pobe pin un- changed (output buffer empty). psobef 0 1 normal. pobe flag as read through pstat register is active-low. table 29. interrupt control (inc) register bit 15 1411 10 9 8 76 54 3 2 1 0 field jint* rsvd obe2 ibf2 time rsvd int[1:0] pibf pobe obe ibf table 30. interrupt status (ins) register bit 15 1411 10 9 8 76 54 3 2 1 0 field jint rsvd obe2 ibf2 time rsvd int[1:0] pibf pobe obe ibf
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 51 5 software architecture (continued) table 31. timerc register bit 157 6 5 4 30 field rsvd disable reload t0en prescale field value description disable 0 1 timer enabled. timer and prescaler disabled. the period register and timer0 are not reset. reload 0 1 timer stops after counting down to 0. timer automatically reloads and repeats indefinitely. t0en 0 1 timer holds current count. timer counts down to 0. prescale see table below. prescale field prescale frequency of timer interrupts prescale frequency of timer interrupts 0000 cko/2 1000 cko/512 0001 cko/4 1001 cko/1024 0010 cko/8 1010 cko/2048 0011 cko/16 1011 cko/4096 0100 cko/32 1100 cko/8192 0101 cko/64 1101 cko/16384 0110 cko/128 1110 cko/32768 0111 cko/256 1111 cko/65536 table 32. phase-locked loop control (pllc) register bit 15 14 13 12 118 75 40 field pllen pllsel icp rsvd lf[3:0] nbits[2:0] mbits[4:0] field value description pllen 0 1 pll powered down. pll powered up. pllsel 0 1 dsp internal clock taken directly from cki. dsp internal clock taken from pll. icp charge pump current selection (see table 64 for proper value). rsvd 0 lf[3:0] loop filter setting (see table 64 for proper value). nbits[2:0] encodes n, 1 n 8, where n = nbits[2:0] + 2, unless nbits[2:0] = 111, then n = 1. mbits[4:0] encodes m, 2 m 20, where m = mbits[4:0] + 2, f internal clock = f cki x (m/(2n)).
data sheet dsp1629 digital signal processor march 2000 52 lucent technologies inc. 5 software architecture (continued) table 33. sbit register bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field direc[7:0] value[7:0] field value description direc 1xxxxxxx iobit7 is an output (input when 0). x1xxxxxx iobit6 is an output (input when 0). xx1xxxxx iobit5 is an output (input when 0). xxx1xxxx iobit4 is an output (input when 0). xxxx1xxx iobit3 is an output (input when 0). xxxxx1xx iobit2 is an output (input when 0). xxxxxx1x iobit1 is an output (input when 0). xxxxxxx1 iobit0 is an output (input when 0). value rxxxxxxx reads the current value of iobit7. xrxxxxxx reads the current value of iobit6. xxrxxxxx reads the current value of iobit5. xxxrxxxx reads the current value of iobit4. xxxxrxxx reads the current value of iobit3. xxxxxrxx reads the current value of iobit2. xxxxxxrx reads the current value of iobit1. xxxxxxxr reads the current value of iobit0. table 34. cbit register bit 1514131211109876543210 field m o d e / m a s k [ 7 : 4 ] m o d e / m a s k [ 3 : 0 ] data / pat [ 7 : 4 ] d ata / pat [ 3 : 0 ] direc[n] * *0 n 7. mode/mask[n] data/pat[n] action 1 (output) 0 0 clear 1 (output) 0 1 set 1 (output) 1 0 no change 1 (output) 1 1 toggle 0 (input) 0 0 no test 0 (input) 0 1 no test 0 (input) 1 0 test for zero 0 (input) 1 1 test for one
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 53 5 software architecture (continued) if the exm pin is high and the int1 is low upon reset, the mwait register is initialized to all 1s (15 wait-states for all external memory). otherwise, the mwait register is initialized to all 0s (0 wait-states) upon reset. table 35. alf register bit 15 14 130 field await lowpr flags field value action await 1 0 power-saving standby mode or standard sleep enabled. normal operation. lowpr 1 0 the internal dpram is addressed beginning at 0x0000 in x space. the internal dpram is addressed beginning at 0xc000 in x space. flags see table below. bit flag use 138 reserved 7 nmns1 not-minus-one from bmu 6 mns1 minus-one from bmu 5 evenp even parity from bmu 4 oddp odd parity from bmu 3 somef some false from bio 2 somet some true from bio 1 allf all false from bio 0 allt all true from bio table 36. mwait register bit 1512 118 74 30 field erom[3:0] eramhi[3:0] io[3:0] eramlo[3:0] table 37. dsp1629 32-bit jtag id register bit 31 30 2928 2719 1812 110 field rsvd secure clock romcode part id 0x03b field value mask-programmable features rsvd 0 secure 0 1 nonsecure rom option. secure rom option. clock 01 11 small-signal input clock option. cmos level input clock option. romcode users romcode id: the romcode id is the 9-bit binary value of the following expression: (20 x value for first letter) + (value of second letter), where the values of the letters are in the following table. for example, romcode gk is (20 x 6) + (9) = 129 or 0 1000 0001. part id 0x29 dsp1629. romcode letter abcdefghjklmnprstuwy value 012345678910111213141516171819
data sheet dsp1629 digital signal processor march 2000 54 lucent technologies inc. 5 software architecture (continued) table 38. ioc register * * the field definitions for the ioc register are different from the dsp1610. bit 15 14 13 12 11 10 9 87 64 30 field rsvd extrom cko2 ebioh werom esio2 siolbc cko[1:0] rsvd denb[3:0] ioc fields ioc field description extrom if 1, sets ab15 low during external memory accesses when werom = 1. cko2 cko configuration (see below). ebioh if 1, enables high half of bio, iobit[4:7], and disables vec[3:0] from pins. werom if 1, allows writing into external program (x) memory. esio2 if 1, enables sio2 and low half of bio, and disables phif from pins. siolbc if 1, do1 and do2 looped back to di1 and di2. cko[1:0] cko configuration (see below). denb3 if 1, delay erom. denb2 if 1, delay eramhi. denb1 if 1, delay io. denb0 if 1, delay eramlo. cko2 cko1 cko0 cko output description 1x pll 0 0 0 cki cki x m/(2n) free-running clock. * , ? * the phase of cki is synchronized by the rising edge of rstb. ? when slowcki is enabled in the powerc register, these options reflect the low-speed internal ring oscillator. 0 0 1 cki/(1 + w) cki x (m/(2n)) / [1 + w] wait-stated clock. * , ? , ? ? the wait-stated clock reflects the internal instruction cycle and may be stretched based on the mwait register setting (see table 36). during sequenced external memory accesses, it completes one cycle. 010 1 1 held high. 0 1 1 0 0 held low. 1 0 0 cki cki output of cki buffer. 1 0 1 cki/(1 + w) cki x (m/(2n)) / [1 + w] sequenced, wait-stated clock.*, ? , ? , ** ** the sequenced wait-stated clock completes two cycles during a sequenced external memory access and may be stretched based on the mwait register setting (see table 36). 110 reserved 111 reserved
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 55 5 software architecture (continued) table 39. powerc register note: the reserved (rsvd) bits should always be written with zeros to make the program compatible with future chip versions. a ? indicates that this bit is unknown on powerup reset and unaffected on subsequent reset. an s indicates that this bit shadows the pc. p indicates the value on an input pin, i.e., the bit in the register reflects the value on the corre- sponding input pin. ? if exm is high and int1 is low when rstb goes high, mwait will contain all ones instead of all zeros. the powerc register configures various power management modes. bit 15 14 13 12 11 10 98 7 6 5 4 30 field xtloff slowcki nock int0en rsvd int1en rsvd sio1dis sio2dis phifdis timerdis rsvd powerc fields field description xtloff 1 = powerdown small-signal clock input. slowcki 1 = select ring oscillator clock (internal slow clock). nock 1 = disable internal processor clock. int0en 1 = int0 clears nock field. int1en 1 = int1 clears nock field. sio1dis 1 = disable sio1. sio2dis 1 = disable sio2. phifdis 1 = disable phif. timerdis 1 = disable timer. table 40. register settings after reset register bits 150 register bits 150 r0 ???????????????? inc 0000000000000000 r1 ???????????????? ins 0000010000000110 r2 ???????????????? sdx2 ???????????????? r3 ???????????????? saddx ???????????????? j ???????????????? cloop 000000000??????? k ???????????????? mwait 0000000000000000 ? rb 0000000000000000 saddx2 ???????????????? re 0000000000000000 sioc2 ??????0000000000 pt ???????????????? cbit ???????????????? pr ???????????????? sbit 00000000pppppppp pi ssssssssssssssss ioc 0000000000000000 i ???????????????? jtag ???????????????? p ???????????????? pl ???????????????? a0 ???????????????? x ???????????????? a0l ???????????????? y ???????????????? a1 ???????????????? yl ???????????????? a1l ???????????????? auc 0000000000000000 timerc ????????00000000 psw ????00?????????? timer0 0000000000000000 c0 ???????????????? tdms2 ??????0000000000 c1 ??????????????? srta2 ???????????????? c2 ???????????????? powerc 0000000000000000 sioc ??????0000000000 pllc 0000000000000000 srta ???????????????? ar0 ???????????????? sdx ???????????????? ar1 ???????????????? tdms ??????0000000000 ar2 ???????????????? phifc 0000000000000000 ar3 ???????????????? pdx0 0000000000000000 ybase ???????????????? alf 00000000????????
data sheet dsp1629 digital signal processor march 2000 56 lucent technologies inc. 5 software architecture (continued) 5.3 instruction set formats this section defines the hardware-level encoding of the dsp1629 device instructions. multiply/alu instructions special function instructions format 1: multiply/alu read/write group field tdsf1xy bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 1a: multiply/alu read/write group field tatsf1xy bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 2: multiply/alu read/write group field tdsf1xy bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 2a: multiply/alu read/write group field tatsf1xy bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 3: f2 alu special functions field tdsf2 con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 3a: f3 alu operations field t d s f3 src2 at 0 1 immediate operand (im16) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 3b: bmu operations field t d s f4[31] 0 f4[0] ar immediate operand (im16) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 57 5 software architecture (continued) control instructions data move instructions cache instructions format 4: branch direct group field tja bit 1514131211109876543210 format 5: branch indirect group field tb reserved0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 6: conditional branch qualifier/software interrupt (icall) note that a branch instruction immediately follows except for a software interrupt (icall). field t si reserved con bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 7: data move group field tat r y/z bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 8: data move (immediate operand2 words) field td r reserved immediate operand (im16) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 9: short immediate group field t i short immediate operand (im9) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 9a: direct addressing field t r/w dr 1 offset bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 format 10: do/redo field tn k bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
data sheet dsp1629 digital signal processor march 2000 58 lucent technologies inc. 5 software architecture (continued) field descriptions table 41. t field table 42. d field table 43. at field table 44. s field table 45. f1 field table 46. x field specifies the type of instruction. t operation format 0000x goto ja 4 00010 short imm j, k, rb, re 9 00011 short imm r0, r1, r2, r3 9 00100 y = a1[l] f1 1 00101 z : at[l] f1 2a 00110 y f1 1 00111 at[l] = y f1 1a 01000 bit 0 = 0, at = r 7 01000 bit 0 = 1, atl = r 7 01001 bit 10 = 0, r = a0 7 01001 bit 10 = 1, r = a0l 7 01010 r = im16 8 01011 bit 10 = 0, r = a1 7 01011 bit 10 = 1, r = a1l 7 01100 y = r 7 01101 z : r 7 01110 do, redo 10 01111 r = y 7 1000x call ja 4 10010 ifc con f2 3 10011 if con f2 3 10100 y = y[l] f1 1 10101 z : y[l] f1 2 10110 x = y f1 1 10111 y[l] = y f1 1 11000 bit 0 = 0, branch indirect 5 11000 bit 0 = 1, f3 alu 3a 11001 y = a0 x = x f1 1 11010 cond. branch qualifier 6 11011 y = a1 x = x f1 1 11100 y = a0[l] f1 1 11101 z : y x = x f1 2 11110 bit 5 = 0, f4 alu (bmu) 3b 11110 bit 5 = 1, direct addressing 9a 11111 y = y x = x f1 1 specifies a destination accumulator. dregister 0 accumulator 0 1 accumulator 1 specifies transfer accumulator. at register 0 accumulator 1 1 accumulator 0 specifies a source accumulator. sregister 0 accumulator 0 1 accumulator 1 specifies the multiply/alu function. f1 operation 0000 ad = pp = x * y 0001 ad = as + pp = x * y 0010 p = x * y 0011 ad = as C pp = x * y 0100 ad = p 0101 ad = as + p 0110 nop 0111 ad = as C p 1000 ad = as | y 1001 ad = as ^ y 1010 as & y 1011 as C y 1100 ad = y 1101 ad = as + y 1110 ad = as & y 1111 ad = as C y specifies the addressing of rom data in two-operand multiply/alu instructions. specifies the high or low half of an accumulator or the y register in one-operand mul- tiply/alu instructions. xoperation two-operand multiply/alu 0 * pt++ 1 * pt++i one-operand multiply/alu 0atl, yl 1ath, yh
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 59 5 software architecture (continued) table 47. y field table 48. z field table 49. f2 field table 50. con field specifies the form of register indirect addressing with postmodification. y operation 0000 * r0 0001 * r0++ 0010 * r0-- 0011 * r0++j 0100 * r1 0101 * r1++ 0110 * r1-- 0111 * r1++j 1000 * r2 1001 * r2++ 1010 * r2-- 1011 * r2++j 1100 * r3 1101 * r3++ 1110 * r3-- 1111 * r3++j specifies the form of register indirect compound ad- dressing with postmodification. zoperation 0000 * r0zp 0001 * r0pz 0010 * r0m2 0011 * r0jk 0100 * r1zp 0101 * r1pz 0110 * r1m2 0111 * r1jk 1000 * r2zp 1001 * r2pz 1010 * r2m2 1011 * r2jk 1100 * r3zp 1101 * r3pz 1110 * r3m2 1111 * r3jk specifies the special function to be performed. f2 operation 0000 ad = as >> 1 0001 ad = as << 1 0010 ad = as >> 4 0011 ad = as << 4 0100 ad = as >> 8 0101 ad = as << 8 0110 ad = as >> 16 0111 ad = as << 16 1000 ad = p 1001 adh = ash + 1 1010 ad = ~as 1011 ad = rnd(as) 1100 ad = y 1101 ad = as + 1 1110 ad = as 1111 ad = C as specifies the condition for special functions and condi- tional control instructions. con condition con condition 00000 mi 01110 true 00001 pl 01111 false 00010 eq 10000 gt 00011 ne 10001 le 00100 lvs 10010 allt 00101 lvc 10011 allf 00110 mvs 10100 somet 00111 mvc 10101 somef 01000 heads 10110 oddp 01001 tails 10111 evenp 01010 c0ge 11000 mns1 01011 c0lt 11001 nmns1 01100 c1ge 11010 npint 01101 c1lt 11011 njint 11100 lock other codes reserved
data sheet dsp1629 digital signal processor march 2000 60 lucent technologies inc. 5 software architecture (continued) table 51. r field table 52. b field table 54. i field table 55. si field specifies the register for data move instructions. r register r register 000000 r0 100000 inc 000001 r1 100001 ins 000010 r2 100010 sdx2 000011 r3 100011 saddx 000100 j 100100 cloop 000101 k 100101 mwait 000110 rb 100110 saddx2 000111 re 100111 sioc2 001000 pt 101000 cbit 001001 pr 101001 sbit 001010 pi 101010 ioc 001011 i 101011 jtag 001100 p 101100 reserved 001101 pl 101101 reserved 001110 pllc 101110 reserved 001111 reserved 101111 reserved 010000 x 110000 a0 010001 y 110001 a0l 010010 yl 110010 a1 010011 auc 110011 a1l 010100 psw 110100 timerc 010101 c0 110101 timer0 010110 c1 110110 tdms2 010111 c2 110111 srta2 011000 sioc 111000 powerc 011001 srta 111001 reserved 011010 sdx 111010 ar0 011011 tdms 111011 ar1 011100 phifc 111100 ar2 011101 pdx0 111101 ar3 011110 reserved 111110 reserved 011111 ybase 111111 alf specifies the type of branch instruction (except software interrupt). b operation 000 return 001 ireturn 010 goto pt 011 call pt 1xx reserved table 53. dr field dr value register 0000 r0 0001 r1 0010 r2 0011 r3 0100 a0 0101 a0l 0110 a1 0111 a1l 1000 y 1001 yl 1010 p 1011 pl 1100 x 1101 pt 1110 pr 1111 psw specifies a register for short immediate data move in- structions. iregister 00 r0/j 01 r1/k 10 r2/rb 11 r3/re specifies when the conditional branch qualifier instruc- tion should be interpreted as a software interrupt in- struction. si operation 0 not a software interrupt 1 software interrupt
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 61 5 software architecture (continued) n field number of instructions to be loaded into the cache. zero implies redo operation. k field number of times the n instructions in cache are to be executed. zero specifies use of value in cloop register. ja field 12-bit jump address. r/w field a zero specifies a write, *(o) = dr. a one specifies a read, dr = *(o). table 56. f3 field table 57. src2 field note: xx encodes the auxiliary register to be used; 00 (ar0), 01(ar1), 10 (ar2), or 11(ar3). specifies the operation in an f3 alu instruction. f3 operation 1000 ad = as[h, l] | {at, im16, p} 1001 ad = as[h, l] ^ {at, im16, p} 1010 as[h, l] & {at, im16, p} 1011 as[h, l] C {at, im16, p} 1101 ad = as[h, l] + {at, im16, p} 1110 ad = as[h, l] & {at, im16, p} 1111 ad = as[h, l] C {at, im16, p} specifies operands in an f3 alu instruction. src2 operands 00 asl, im16 10 ash, im16 01 as, at 11 as, p table 58. bmu encodings f4 ar operation 0000 00xx ad = as >> arm 0001 00xx ad = as << arm 0000 10xx ad = as >>> arm 0001 10xx ad = as <<< arm 1000 0000 ad = as >> as 1001 0000 ad = as << as 1000 1000 ad = as >>> as 1001 1000 ad = as <<< as 1100 0000 ad = as >> im16 1101 0000 ad = as << im16 1100 1000 ad = as >>> im16 1101 1000 ad = as <<< im16 0000 1100 ad = exp(as) 0001 11xx ad = norm(as, arm) 1110 0000 ad = extracts(as, im16) 0010 00xx ad = extracts(as, arm) 1110 0100 ad = extractz(as, im16) 0010 01xx ad = extractz(as, arm) 1110 1000 ad = insert(as, im16) 1010 10xx ad = insert(as, arm) 0111 0000 ad = as:aa0 0111 0001 ad = as:aa1
data sheet dsp1629 digital signal processor march 2000 62 lucent technologies inc. 6 signal descriptions figure 9. dsp1629 pinout by interface external memory interface io eramhi erom exm ab[15:0] db[15:0] rwn system interface or control i/o interface obe1 old1 ock1 do1 tdi tdo tck tms pods or old2 pstat or do2 pcsn or ock2 pobe or obe2 pbsel or sync2 pb2 or doen2 pibf or ibf2 pids or ild2 pb0 or ick2 pb1 or di2 pb3 or sadd2 pb[7:4] or iobit[3:o] dsp1629 rstb cko iack stop cki2 vec[3:0] or iobit[4:7] int[1:0] parallel host interface or serial interface #2 and control i/o interface ild1 di1 trap serial interface #1 ick1 ibf1 sync1 eramlo sadd1 doen1 jtag test interface 2 4 16 16 4 cki trst dsel 5-4006 (f).i figure 9 shows the pinout for the dsp1629. the signals can be separated into five interfaces as shown. these interfaces and the signals that comprise them are de- scribed below. 6.1 system interface the system interface consists of the clock, interrupt, and reset signals for the processor. rstb reset: negative assertion. a high-to-low transition causes the processor to enter the reset state. the auc, powerc, sioc, sioc2, phifc, pdx0, tdms, tdms2, timerc, timer0, sbit (upper byte), inc, ins (except obe, obe2, and pods status bits set), alf (upper 2 bits, await and lowpr), ioc, rb, and re registers are cleared. the mwait register is initialized to all 0s (zero wait-states) unless the exm pin is high and the int1 pin is low. in that case, the mwait register is initialized to all 1s (15 wait-states). reset clears iack, vec[3:0]/iobit[4:7], ibf, and ibf2. the dau condition flags are not affected by reset. iobit[7:0] are initialized as inputs. if any of the iobit pins are switched to outputs (by writing sbit), their initial value will be logic zero (see table 40, register settings after reset). upon negation of the signal, the processor begins exe- cution at location 0x0000 in the active memory map (see section 4.4, memory maps and wait-states).
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 63 6 signal descriptions (continued) cki input clock: a mask-programmable option selects one of three possible input buffers for the cki pin (see sec- tion 7, mask-programmable options, and table 1, pin descriptions). the internal cki from the output of the selected input buffer can then drive the internal proces- sor clock directly (1x) or drive the on-chip pll (see sec- tion 4.13). the pll allows the cki input clock to be at a lower frequency than the internal processor clock. cki2 input clock 2: used with mask-programmable input clock options which require an external small signal dif- ferential across cki and cki2 (see table 1, pin de- scriptions). when the cmos option is selected, this pin should be tied to v ssa . stop stop input clock: negative assertion. a high-to-low transition synchronously stops all of the internal proces- sor clocks leaving the processor in a defined state. re- turning the pin high will synchronously restart the processor clocks to continue program execution from where it left off without any loss of state. this hardware feature has the same effect as setting the nock bit in the powerc register (see table 39). cko clock out: buffered output clock with options program- mable via the ioc register (see table 38). the selectable cko options (see tables 38 and 29) are as follows: n a free-running output clock at the frequency of the in- ternal processor clock; runs at the internal ring oscil- lator frequency when slowcki is enabled. n a wait-stated clock based on the internal instruction cycle; runs at the internal ring oscillator frequency when slowcki is enabled. n a sequenced, wait-stated clock based on the emi se- quencer cycle; runs at the internal ring oscillator fre- quency when slowcki is enabled. n a free-running output clock that runs at the cki rate, independent of the powerc register setting. this op- tion is only available with the small-signal clock op- tions. when the pll is selected, the cko frequency equals the input cki frequency regardless of how the pll is programmed. n a logic 0. n a logic 1. int[1:0] processor interrupts 0 and 1: positive assertion. hardware interrupt inputs to the dsp1629. each is en- abled via the inc register. when enabled and asserted, each cause the processor to vector to the memory loca- tion described in table 4. int1 is used in conjunction with exm to select the desired reset initialization of the mwait register (see table 36). when both int0 and rstb are asserted, all output and bidirectional pins (ex- cept tdo, which 3-states by jtag control) are put in a 3-state condition. vec[3:0] interrupt output vector: these four pins indicate which interrupt is currently being serviced by the device. table 4 shows the code associated with each interrupt condition. vec[3:0] are multiplexed with iobit[4:7]. iack interrupt acknowledge: positive assertion. iack signals when an interrupt is being serviced by the dsp1629. iack remains asserted while in an interrupt service routine, and is cleared when the ireturn instruc- tion is executed. trap trap signal: positive assertion. when asserted, the processor is put into the trap condition, which normally causes a branch to the location 0x0046. the hardware development system (hds) can configure the trap pin to cause an hds trap, which causes a branch to loca- tion 0x0003. although normally an input, the pin can be configured as an output by the hds. as an output, the pin can be used to signal an hds breakpoint in a multi- ple processor environment.
data sheet dsp1629 digital signal processor march 2000 64 lucent technologies inc. 6 signal descriptions (continued) 6.2 external memory interface the external memory interface is used to interface the dsp1629 to external memory and i/o devices. it sup- ports read/write operations from/to program and data memory spaces. the interface supports four external memory segments. each external memory segment can have an independent number of software-program- mable wait-states. one hardware address is decoded, and an enable line is provided, to allow glueless i/o in- terfacing. ab[15:0] external memory address bus: output only. this 16- bit bus supplies the address for read or write operations to the external memory or i/o. during external memory accesses, ab[15:0] retain the value of the last valid ex- ternal access. db[15:0] external memory data bus: this 16-bit bidirectional data bus is used for read or write operations to the ex- ternal memory or i/o. rwn read/write not: when a logic 1, the pin indicates that the memory access is a read operation. when a logic 0, the memory access is a write operation. exm external memory select: input only. this signal is latched into the device on the rising edge of rstb. the value of exm latched in determines whether the internal rom is addressable in the instruction/coefficient mem- ory map. if exm is low, internal rom is addressable. if exm is high, only external rom is addressable in the instruction/coefficient memory map (see table 5, in- struction/coefficient memory maps). exm chooses be- tween map1 or map2 and between map3 or map4. erom external rom enable signal: negative assertion. when asserted, the signal indicates an access to exter- nal program memory (see table 5, instruction/coeffi- cient memory maps). this signal's leading edge can be delayed via the ioc register (see table 38). eramhi external ram high enable signal: negative asser- tion. when asserted, the signal indicates an access to external data memory addresses 0x8000 through 0xffff (see table 6, data memory map). this signal's leading edge can be delayed via the ioc register (see table 38). eramlo external ram low enable signal: negative asser- tion. when asserted, the signal indicates an access to external data memory addresses 0x4100 through 0x7fff (see table 6, data memory map). this signal's leading edge can be delayed via the ioc register (see table 38). io external i/o enable signal: negative assertion. when asserted, the signal indicates an access to external data memory addresses 0x4000 through 0x40ff (see table 6, data memory map). this memory segment is intended for memory-mapped i/o. this signal's leading edge can be delayed via the ioc register (see table 38).
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 65 6 signal descriptions (continued) 6.3 serial interface #1 the serial interface pins implement a full-featured syn- chronous/asynchronous serial i/o channel. in addition, several pins offer a glueless tdm interface for multipro- cessing communication applications (see figure 6, mul- tiprocessor communications and connections). di1 data input: serial data is latched on the rising edge of ick1, either lsb or msb first, according to the sioc reg- ister msb field (see table 22). ick1 input clock: the clock for serial input data. in active mode, ick1 is an output; in passive mode, ick1 is an input, according to the sioc register ick field (see table 22). input has typically 0.7 v hysteresis. ild1 input load: the clock for loading the input buffer, sdx[in], from the input shift register isr. a falling edge of ild1 indicates the beginning of a serial input word. in active mode, ild1 is an output; in passive mode, ild1 is an input, according to the sioc register ild field (see table 22). input has typically 0.7 v hysteresis. ibf1 input buffer full: positive assertion. ibf1 is asserted when the input buffer, sdx[in], is filled. ibf1 is negated by a read of the buffer, as in a0 = sdx. ibf1 is also ne- gated by asserting rstb. do1 data output: the serial data output from the output shift register (osr), either lsb or msb first (according to the sioc register msb field). do1 changes on the rising edges of ock1. do1 is 3-stated when doen1 is high. doen1 data output enable: negative assertion. an input when not in the multiprocessor mode. do1 and sadd1 are enabled only if doen1 is low. doen1 is bidirection- al when in the multiprocessor mode (tdms register mode field set). in the multiprocessor mode, doen1 indicates a valid time slot for a serial output. ock1 output clock: the clock for serial output data. in active mode, ock1 is an output; in passive mode, ock1 is an input, according to the sioc register ock field (see ta- ble 22). input has typically 0.7 v hysteresis. old1 output load: the clock for loading the output shift reg- ister, osr, from the output buffer sdx[out]. a falling edge of old1 indicates the beginning of a serial output word. in active mode, old1 is an output; in passive, old1 is an input, according to the sioc register old field (see table 22). input has typically 0.7 v hysteresis. obe1 output buffer empty: positive assertion. obe1 is as- serted when the output buffer, sdx[out], is emptied (moved to the output shift register for transmission). it is cleared with a write to the buffer, as in sdx = a0. obe1 is also set by asserting rstb. sadd1 serial address: negative assertion. a 16-bit serial bit stream typically used for addressing during multiproces- sor communication between multiple dsp16xx devices. in multiprocessor mode, sadd1 is an output when the tdms time slot dictates a serial transmission; otherwise, it is an input. both the source and destination dsp can be identified in the transmission. sadd1 is always an output when not in multiprocessor mode and can be used as a second 16-bit serial output. see the dsp1611/17/18/27 digital signal processor informa- tion manual for additional information. sadd1 is 3- stated when doen1 is high. when used on a bus, sadd1 should be pulled high through a 5 k w w w w resistor. sync1 multiprocessor synchronization: typically used in the multiprocessor mode, a falling edge of sync1 indi- cates the first word (time slot 0) of a tdm i/o stream and causes the resynchronization of the active ild1 and old1 generators. sync1 is an output when the tdms register sync field is set (i.e., selects the master dsp and uses time slot 0 for transmit). as an input, sync1 must be tied low unless part of a tdm interface. when used as an output, sync1 = [ild1/old1]/8 or 16, depending on the setting of the syncsp field of the tdms register. when configured as described above, sync1 can be used to generate a slow clock for sio operations. input has typically 0.7 v hysteresis.
data sheet dsp1629 digital signal processor march 2000 66 lucent technologies inc. 6 signal descriptions (continued) 6.4 parallel host interface or serial interface #2 and control i/o interface this interface pin multiplexes a parallel host interface with a second serial i/o interface and a 4-bit i/o inter- face. the interface selection is made by writing the esio2 bit in the ioc register (see table 38 and section 4.1). the functions and signals for the second sio cor- respond exactly with those in sio #1. therefore, the pin descriptions below discuss only phif and bio pin func- tionality. pb[7:0] parallel i/o data bus: this 8-bit bidirectional bus is used to input data to, or output data from, the phif. note that pb[3:0] are pin multiplexed with sio2 func- tionality, and pb[7:4] are pin multiplexed with bio unit pins iobit[3:0] (see section 4.1). pcsn peripheral chip select not: negative assertion. pcsn is an input. while pcsn is low, the data strobes pids and pods are enabled. while pcsn is high, the dsp1629 ignores any activity on pids and pods. pbsel peripheral byte select: an input pin, configurable in software. selects the high or low byte of pdx0 available for host accesses. pstat peripheral status select: pstat is an input. when a logic 0, the phif will output the pdx0[out] register on the pb bus. when a logic 1, the phif will output the con- tents of the pstat register on pb[7:0]. pids parallel input data strobe: an input pin, software con- figurable to support both intel and motorola protocols. in intel mode: negative assertion. pids is pulled low by an external device to indicate that data is available on the pb bus. the dsp latches data on the pb bus on the rising edge (low-to-high transition) of pids or pcsn, whichever comes first. in motorola mode: pids/prwn functions as a read/ write strobe. the external device sets pids/prwn to a logic 0 to indicate that data is available on the pb bus (write operation by the external device). a logic 1 on pids/prwn indicates an external read operation by the external device. pods parallel output data strobe: an input pin, software configurable to support both intel and motorola proto- cols. in intel mode: negative assertion. when pods is pulled low by an external device, the dsp1629 places the con- tents of the parallel output register, pdx0, onto the pb bus. in motorola mode: software-configurable assertion lev- el. the external device uses pods/pds as its data strobe for both read and write operations. pibf parallel input buffer full: an output pin with positive assertion; configurable in software. this flag is cleared after reset, indicating an empty input buffer pdx0[in]. pibf is set immediately after the rising edge of pids or pcsn, indicating that data has been latched into the pdx0[in] register. when the dsp1629 reads the con- tents of this register, emptying the buffer, the flag is cleared. configured in software, pibf may become the logical or of the pibf and pobe flags. pobe parallel output buffer empty: an output pin with pos- itive assertion; configurable in software. this flag is set after reset, indicating an empty output buffer pdx0[out]. pobe is set immediately after the rising edge of pods or pcsn, indicating that the data in pdx0[out] has been driven onto the pb bus. when the dsp1629 writes to pdx0[out], filling the buffer, this flag is cleared. 6.5 control i/o interface this interface is used for status and control operations provided by the bit i/o unit of the dsp1629. it is pin mul- tiplexed with the phif and vec[3:0] pins (see section 4.1). setting the esio2 and ebioh bits in the ioc regis- ter provides a full 8-bit bio interface at the associated pins. iobit[7:0] i/o bits [7:0]: each of these bits can be independently configured as either an input or an output. as outputs, they can be independently set, toggled, or cleared. as inputs, they can be tested independently or in combina- tions for various data patterns.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 67 6 signal descriptions (continued) 6.6 jtag test interface the jtag test interface has features that allow pro- grams and data to be downloaded into the dsp via four pins. this provides extensive test and diagnostic capa- bility. in addition, internal circuitry allows the device to be controlled through the jtag port to provide on-chip in-circuit emulation. lucent technologies provides hardware and software tools to interface to the on-chip hds via the jtag port. note: the dsp1629 provides all jtag/ ieee 1149.1 standard test capabilities including boundary scan. see the dsp1611/17/18/27 digital signal processor information manual for additional in- formation on the jtag test interface. tdi test data input: jtag serial input signal. all serial- scanned data and instructions are input on this pin. this pin has an internal pull-up resistor. tdo test data output: jtag serial output signal. serial- scanned data and status bits are output on this pin. tms test mode select: jtag mode control signal that, when combined with tck, controls the scan operations. this pin has an internal pull-up resistor. tck test clock: jtag serial shift clock. this signal clocks all data into the port through tdi, and out of the port through tdo, and controls the port by latching the tms signal inside the state-machine controller. trst test reset: negative assertion. jtag test reset. when asserted low, asynchronously resets jtag tap con- troller. in an application environment, this pin must be asserted prior to or concurrent with rstb. this pin has an internal pull-up resistor.
data sheet dsp1629 digital signal processor march 2000 68 lucent technologies inc. 7 mask-programmable options the dsp1629 contains a rom that is mask-programmable. the selection of several programmable features is made when a custom rom is encoded. these features select the input clock options, the instruction/coefficient memory map option, and the hardware emulation or rom security option, as summarized in table 59. 7.1 input clock options for all input options, the input clock cki can run at some fraction of the internal clock frequency by setting the pll multiplication factors appropriately (see section 4.12, clock synthesis). when the pll is bypassed, the input clock cki frequency is the internal clock frequency. 7.2 memory map options the dsp1629 offers a dsp1629x16 or a dsp1629x10 where the difference is in the memory maps. the dsp1629x16 contains 16 kwords of internal ram (dpram). the dsp1629x10 supports the use of only 10 kwords of dpram. see section 4.4 memory maps and wait-states for further description. 7.3 rom security options the dsp1600 hardware development system (hds) provides on-chip in-circuit emulation and requires that the re- locatable hds code be linked to the application code. this code's object file is called 1629hds.v # , where # is a unique version identifier. refer to the dsp1629-st software tools release for more specific information. if on-chip in-circuit emulation is desired, a nonsecure rom must be chosen. if rom security is desired with the dsp1629, the hds cannot be used. to provide testing of the internal rom contents on a secure rom device, a cyclic redundancy check (crc) program is called by and linked with the user's source code. the crc code resides in the first 4 kwords of rom. see the dsp1600 support tools manual for more detailed information. table 59. dsp1629 rom options features options comments input clock cmos level small signal 2.7 v and 3 v 2.7 v and 3 v memory map dsp1629x16 dsp1629x10 16 kwords dpram 10 kwords dpram rom security nonsecure secure specify and link 1629hds.v # * , allows emulation. specify and link crc16.v # ? , no emulation capability. * 1629hds.v # (# indicates the current version number) is the relocatable hds object code. it uses approximately 140 words and must reside in the first 4 kwords of rom. ? crc16.v # is the cyclic redundancy check object code. it uses approximately 75 words and must reside in the first 4 kwords of rom. see the dsp1600 support tools manual for detailed information.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 69 8 device characteristics 8.1 absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. external leads can be bonded and soldered safely at temperatures of up to 300 c. (tbd for 144-pin pbga) voltage range on v dd with respect to ground using devices designed for 3 v operation .............................................................................................................. ................C0.5 v to +4.6 v voltage range on any pin ............................................................................................. v ss C 0.5 v to v dd + 0.5 v power dissipation.............................................................................................................. .................................. 1 w ambient temperature range ...................................................................................................... ... C40 c to +85 c storage temperature range .................................................................................................................... C 65 c to +150 c 8.2 handling precautions all mos devices must be handled with certain precautions to avoid damage due to the accumulation of static charge. although input protection circuitry has been incorporated into the devices to minimize the effect of this static buildup, proper precautions should be taken to avoid exposure to electrostatic discharge during handling and mount- ing. lucent technologies employs a human-body model for esd-susceptibility testing. since the failure voltage of electronic devices is dependent on the current, voltage, and hence, the resistance and capacitance, it is important that standard values be employed to establish a reference by which to compare test data. values of 100 pf and 1500 w are the most common and are the values used in the lucent technologies human-body model test circuit. the breakdown voltage for the dsp1629 is greater than 2000 v. 8.3 recommended operating conditions the ratio of the instruction cycle rate to the input clock frequency is 1:1 without the pll (referred to as 1x operation) and m/(2n) with the pll selected (see section 4.12). device speeds greater than 50 mips do not support 1x operation; use the pll. table 60. recommended operating conditions maximum instruction rate (mips) device speed input clock package supply voltage v dd (v) ambient temperature t a ( c) min max min max 52 19.2 ns cmos, small-signal pbga bqfp or tqfp 2.73.3C4085 80 12.5 ns cmos, small-signal pbga bqfp or tqfp 2.73.3C4085 60 16.7 ns cmos, small-signal pbga bqfp or tqfp 3.03.6C4085 100 10 ns cmos, small-signal pbga bqfp or tqfp 3.03.6C4085
data sheet dsp1629 digital signal processor march 2000 70 lucent technologies inc. 8 device characteristics (continued) 8.4 package thermal considerations the recommended operating temperature specified above is based on the maximum power, package type, and maximum junction temperature. the following equations describe the relationship between these parameters. if the applications' maximum power is less than the worst-case value, this relationship determines a higher maximum am- bient temperature or the maximum temperature measured at top dead center of the package. t a = t j C p x q q q q ja t tdc = t j C p x q q q q j-tdc where t a is the still-air ambient temperature and t tdc is the temperature measured by a thermocouple at the top dead center of the package. maximum junction temperature (t j ) in 100-pin bqfp ..................................................................................100 c 100-pin bqfp maximum thermal resistance in still-air-ambient ( q ja ) ..................................................... 55 c/w 100-pin bqfp maximum thermal resistance, junction to top dead center ( q j-tdc )............................... 12 c/w maximum junction temperature (t j ) in 100-pin tqfp ..................................................................................100 c 100-pin tqfp maximum thermal resistance in still-air-ambient ( q ja ) ..................................................... 30 c/w 100-pin tqfp maximum thermal resistance, junction to top dead center ( q j-tdc ) ................................. 6 c/w maximum junction temperature (t j ) in 144-pin pbga..................................................................................100 c 144-pin pbga maximum thermal resistance in still-air-ambient ( q ja ) .......................... tbd (estimated 30 c/w) 144-pin pbga maximum thermal resistance, junction to top dead center ( q j-tdc )..................................... tbd warning: due to package thermal constraints, proper precautions in the user's application should be tak- en to avoid exceeding the maximum junction temperature of 100 c. otherwise, the device will be affected adversely.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 71 9 electrical characteristics and requirements the following electrical characteristics are preliminary and are subject to change. electrical characteristics refer to the behavior of the device under specified conditions. electrical requirements refer to conditions imposed on the user for proper operation of the device. the parameters below are valid for the conditions described in section 8.3, recommended operating conditions. table 61. electrical characteristics and requirements parameter symbol min max unit input voltage: low v il C0.3 0.3 * v dd v high v ih 0.7 * v dd v dd + 0.3 v input current (except tms, tdi): low (v il = 0 v, v dd = 5.25 v) i il C5 m a high (v ih = 5.25 v, v dd = 5.25 v) i ih 5 m a input current (tms, tdi): low (v il = 0 v, v dd = 5.25 v) i il C100 m a high (v ih = 5.25 v, v dd = 5.25 v) i ih 5 m a output low voltage: low (i ol = 2.0 ma) v ol 0.4 v low (i ol = 50 m a) v ol 0.2 v output high voltage: high (i oh = C2.0 ma) v oh v dd C 0.7 v high (i oh = C50 m a) v oh v dd C 0.2 v output 3-state current: low (v dd = 5.25 v, v il = 0 v) i ozl C10 m a high (v dd = 5.25 v, v ih = 5.25 v) i ozh 10 m a input capacitance ci 5 pf table 62. electrical requirements for mask-programmable input clock options parameter symbol min max unit cki cmos level input voltage: low high v il v ih C0.3 0.7 * v dd 0.3 * v dd v dd + 0.3 v v small-signal peak-to-peak voltage (on cki) * * the small-signal buffer must be used in single-ended mode where an ac waveform (sine or square) is applied to cki and a dc voltage approximately equal to the average value of cki is applied to cki2, as shown in the figure below. the maximum allowable ripple on cki2 is 100 mv. vpp 0.6 v small-signal input duty cycle ? ? duty cycle for a sine wave is defined as the percentage of time during each clock cycle that the voltage on cki exceeds the vo ltage on cki2. dcyc 45 55 % small-signal input voltage range (pins: cki, cki2) vin 0.2 * v dd 0.6 * v dd v small-signal buffer frequency range fss 35 mhz cki cki2
data sheet dsp1629 digital signal processor march 2000 72 lucent technologies inc. 9 electrical characteristics and requirements (continued) table 63. pll electrical specifications, vco frequency ranges parameter symbol min max unit vco frequency range (v dd = 3 v 10%) * * the m and n counter values in the pllc register must be set so that the vco will operate in the appropriate range (see table 63). choose the lowest value of n and then the appropriate value of m for f internal clock = f cki x (m/(2n)) = f vco /2. f vco 50 160 mhz vco frequency range (v dd = 3.0 v C 3.6 v) f vco 50 200 mhz input jitter at cki 200 ps-rms table 64. pll electrical specifications and pllc register settings mv dd pllc13 (icp) pllc12 reserved pllc[11:8] (lf[3:0]) typical lock-in time ( m m m m s) * * lock-in time represents the time following assertion of the pllen bit of the pllc register during which the pll output clock is unstable. the dsp must operate from the 1x cki input clock or from the slow ring oscillator while the pll is locking. completion of the lock- in interval is indicated by assertion of the lock flag. 2324 2.7 v C 3.6 v 1 0 1011 30 2122 2.7 v C 3.6 v 1 0 1010 30 1920 2.7 v C 3.6 v 1 0 1001 30 1618 2.7 v C 3.6 v 1 0 1000 30 1215 2.7 v C 3.6 v 1 0 0111 30 811 2.7 v C 3.6 v 1 0 0110 30 27 2.7 v C 3.6 v 1 0 0100 30
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 73 9 electrical characteristics and requirements (continued) figure 10. plot of v oh vs. i oh under typical operating conditions figure 11. plot of v ol vs. i ol under typical operating conditions 0 10203040 51525354550 device under test i oh (ma) v oh (v) v dd C 0.1 v dd C 0.2 v dd C 0.3 v dd C 0.4 v dd i oh v oh 5-4007 (f).a 5-4008 (f).b device under test i ol v ol 0.4 0.3 0.2 0.1 0 v ol (v) 0 5 10 15 20 25 30 35 40 45 50 i ol (ma)
data sheet dsp1629 digital signal processor march 2000 74 lucent technologies inc. 9 electrical characteristics and requirements (continued) 9.1 power dissipation power dissipation is highly dependent on dsp program activity and the frequency of operation. the typical power dissipation listed is for a selected application. the following electrical characteristics are preliminary and are subject to change. * t = cki clock cycle for 1x input clock option or t = cki clock cycle divided by m/(2n) for pll clock option (see section 4.12) . ? t l = pll lock time (see table 64). table 65. power dissipation and wake-up latency operating mode (unused inputs at vdd or vss) vdd= typical power dissipation (mw) wake-up latency i/o units on powerc[7:4] = 0x0 i/o units off powerc[7:4] = 0xf (pll not used during wake state) (pll used during wake state) 3 v 3 v 3 v 3 v normal operation ioc = 0x0180 pll disabled cki & cko = 40 mhz cmos 93.7 91.2 small signal 96.3 93.7 cki & cko = 0 mhz cmos 0.17 0.17 small signal 2.75 2.75 normal operation ioc = 0x0180 pll enabled pllc = 0xfc0e cki = 10 mhz cko = 40 mhz cmos 96.7 94.2 small signal 99.3 96.7 power management modes cko = 40 mhz standard sleep, external interrupt alf[15] = 1, ioc = 0x0180 pll disabled during sleep cmos 14.0 9.3 3t* 3t* + t l ? small signal 16.3 12.0 3t* 3t* + t l ? standard sleep, external interrupt alf[15] = 1, ioc = 0x0180 pll enabled during sleep cmos 16.5 11.2 3t* small signal 18.9 14.0 3t* sleep with slow internal clock small signal enabled powerc[15:14] = 01, alf[15] = 1, ioc = 0x0180 pll disabled during sleep cmos 0.7 0.5 5.0 m s 5.0 m s + t l ? small signal 3.7 3.5 5.0 m s 5.0 m s + t l ? sleep with slow internal clock small signal enabled powerc[15:14] = 01, alf[15] = 1, ioc = 0x0180 pll enabled during sleep cmos 3.3 2.9 5.0 m s small signal 6.1 5.5 5.0 m s
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 75 9 electrical characteristics and requirements (continued) * t = cki clock cycle for 1x input clock option or t = cki clock cycle divided by m/(2n) for pll clock option (see section 4.12) . ? t l = pll lock time (see table 64). the power dissipation listed is for internal power dissipation only. total power dissipation can be calculated on the basis of the application by adding c x v dd /2 x f for each output, where c is the additional load capacitance and f is the output frequency. power dissipation due to the input buffers is highly dependent on the input voltage level. at full cmos levels, es- sentially no dc current is drawn. however, for levels between the power supply rails, especially at or near the thresh- old of v dd /2, high currents can flow. although input and i/o buffers may be left untied (since the input voltage levels of the input and i/o buffers are designed to remain at full cmos levels when not driven by the dsp), it is still rec- ommended that unused input and i/o pins be tied to v ss or v dd through a 10 k w resistor to avoid application am- biguities. further, if i/o pins are tied high or low, they should be pulled fully to v ss or v dd . warning: the device needs to be clocked for at least six cki cycles during reset after powerup. other- wise, high currents may flow. table 65. power dissipation and wake-up latency (continued) operating mode (unused inputs at v dd or v ss ) v dd = typical power dissipation (mw) wake-up latency i/o units on powerc[7:4] = 0x0 i/o units off powerc[7:4] = 0xf (pll not used during wake state) (pll used during wake state) 3 v 3 v 3 v 3 v sleep with slow internal clock small signal disabled powerc[15:14] = 11, alf[15] = 1, ioc = 0x0180 pll disabled during sleep small signal 0.40 0.30 20 m s 20 m s + t l ? software stop powerc[15:12] = 0011 pll disabled during stop cmos 0.060 0.060 3t* 3t* + t l ? software stop powerc[15:12] = 1111 pll disabled during stop small signal 0.060 0.060 20 m s 20 m s + t l ? hardware stop (stop = v ss ) powerc[15:12] = 0000 pll disabled during stop cmos 0.060 0.060 3t* small signal 1.20 1.20 3t* hardware stop (stop = v ss ) powerc[15:12] = 0000 pll enabled during stop cmos 2.5 2.5 3t* 3t* small signal 3.6 3.6 3t* 3t*
data sheet dsp1629 digital signal processor march 2000 76 lucent technologies inc. 10 timing characteristics for 3.0 v operation the following timing characteristics and requirements are preliminary information and are subject to change. timing characteristics refer to the behavior of the device under specified conditions. timing requirements refer to conditions imposed on the user for proper operation of the device. all timing data is valid for the following conditions: t a = C40 c to +85 c (see section 8.3.) v dd = 3.0 v to 3.6 v, v ss = 0 v (see section 8.3.) capacitance load on outputs (c l ) = 50 pf, except for cko, where c l = 20 pf. output characteristics can be derated as a function of load capacitance (c l ). all outputs: 0.03 ns/pf dt/dc l 0.07 ns/pf for 10 c l 100 pf at v ih for rising edge and at v il for falling edge. for example, if the actual load capacitance is 30 pf instead of 50 pf, the derating for a rising edge is (30 C 50) pf x 0.06 ns/pf = 1.2 ns less than the specified rise time or delay that includes a rise time. test conditions for inputs: n rise and fall times of 4 ns or less n timing reference levels for delays = v ih , v il test conditions for outputs (unless noted otherwise): n c load = 50 pf; except for cko, where c load = 20 pf n timing reference levels for delays = v ih , v il n 3-state delays measured to the high-impedance state of the output driver for the timing diagrams, see table 62 for input clock requirements. unless otherwise noted, cko in the timing diagrams is the free-running cko.
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 77 10 timing characteristics for 3.0 v operation (continued) 10.1 dsp clock generation * see table 62 for input clock electrical requirements. ? free-running clock. ? wait-stated clock (see table 38). w = number of wait-states. figure 12. i/o clock timing diagram ? device speeds greater than 50 mips do not support 1x operation. use the pll. ? device is fully static, t1 is tested at 100 ns for 1x input clock option, and memory hold time is tested at 0.1 s. ? t = internal clock period, set by cki or by cki and the pll parameters. table 66. timing requirements for input clock abbreviated reference parameter min max unit t1 clock in period (high to high) 20 ? ? ns t2 clock in low time (low to high) 10 ns t3 clock in high time (high to low) 10 ns table 67. timing characteristics for input clock and output clock abbreviated reference parameter min max unit t4 clock out high delay 10 ns t5 clock out low delay (high to low) 10 ns t6 clock out period (low to low) t ? ns t6a clock out period with slowcki bit set in powerc register (low to low) 0.74 3.8 m s 5-4009 (f).a t4 t1 t2 1x cki* t5 cko ? t3 t6, t6a cko ? external memory cycle w = 1
data sheet dsp1629 digital signal processor march 2000 78 lucent technologies inc. 10 timing characteristics for 3.0 v operation (continued) 10.2 reset circuit the dsp1629 has two external reset pins: rstb and trst. at initial powerup, or if the supply voltage falls below v dd min* and a device reset is required, both trst and rstb must be asserted to initialize the device. figure 13 shows two separate events: n chip reset at initial powerup. n chip reset following a drop in power supply. note: the trst pin must be asserted even if the jtag controller is not used by the application. * see table 60, recommended operating conditions. * when both int0 and rstb are asserted, all output and bidirectional pins (except tdo, which 3-states by jtag control) are put i n a 3-state condition. with rstb asserted and int0 not asserted, erom, eramhi, eramlo, io, and rwn outputs remain high, and cko remains a free-running clock. ? see table 62 for input clock electrical requirements. figure 13. powerup reset and chip reset timing diagram note: the device needs to be clocked for at least six cki cycles during reset after powerup. otherwise, high cur- rents may flow. table 68. timing requirements for powerup reset and chip reset abbreviated reference parameter min max unit t8 rstb and trst reset pulse (low to high) 6t ns t9 v dd ramp 10 ms t146 v dd min to rstb low cmos small-signal 2t 20 ns m s t153 rstb (low to high) 54 ns table 69. timing characteristics for powerup reset and chip reset abbreviated reference parameter min max unit t10 rstb disable time (low to 3-state) 100 ns t11 rstb enable time (high to valid) 100 ns v dd ramp rstb, trst output pins * cki ? t11 v oh v ol v ih v il t9 t146 t10 0.4 v v dd min t11 v dd min 0.4 v t10 t9 t146 t153 t8 t153 t8 5-4010 (f).a
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 79 10 timing characteristics for 3.0 v operation (continued) 10.3 reset synchronization * see table 62 for input clock electrical requirements. notes: cko 1 and cko 2 are two possible cko states before reset. cko is free-running. if the rising edge of rstb (low to high) is captured instead by the falling edge of cko (high to low), cko and cki will be in-p hase at t5 + 2 x t6. figure 14. reset synchronization timing table 70. timing requirements for reset synchronization timing abbreviated reference parameter min max unit t126 reset setup (high to high) 3 t/2 C 1 ns 5-4011 (f).a cki * v ih v il t126 t5 + 2 x t6 rstb v ih v il v ih v il cko v ih v il cko
data sheet dsp1629 digital signal processor march 2000 80 lucent technologies inc. 10 timing characteristics for 3.0 v operation (continued) 10.4 jtag i/o specifications figure 15. jtag timing diagram table 71. timing requirements for jtag input/output abbreviated reference parameter min max unit t12 tck period (high to high) 50 ns t13 tck high time (high to low) 22.5 ns t14 tck low time (low to high) 22.5 ns t155 tck rise transition time (low to high) 0.6 v/ns t156 tck fall transition time (high to low) 0.6 v/ns t15 tms setup time (valid to high) 7.5 ns t16 tms hold time (high to invalid) 2 ns t17 tdi setup time (valid to high) 7.5 ns t18 tdi hold time (high to invalid) 2 ns table 72. timing characteristics for jtag input/output abbreviated reference parameter min max unit t19 tdo delay (low to valid) 19 ns t20 tdo hold (low to invalid) 0 ns t12 t14 t13 t15 t16 t17 t18 t19 t20 tck tms tdi tdo v ih v il v ih v il v ih v il v oh v ol t155 t156 5-4017 (f)
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 81 10 timing characteristics for 3.0 v operation (continued) 10.5 interrupt * cko is free-running. ? iack assertion is guaranteed to be enclosed by vec[3:0] assertion. figure 16. interrupt timing diagram note: interrupt is asserted during an interruptible instruction and no other pending interrupts. note: interrupt is asserted during an interruptible instruction and no other pending interrupts. table 73. timing requirements for interrupt abbreviated reference parameter min max unit t21 interrupt setup (high to low) 19 ns t22 int assertion time (high to low) 2t ns table 74. timing characteristics for interrupt abbreviated reference parameter min max unit t23 iack assertion time (low to high) t/2 + 10 ns t24 vec assertion time (low to high) 12.5 ns t25 iack invalid time (low to low) 10 ns t26 vec invalid time (low to low) 12.5 ns 5-4018 (f) cko * int[1:0] t21 v oh v ol v ih v il t22 iack ? v oh v ol vec[3:0] v oh v ol t23 t24 t25 t26
data sheet dsp1629 digital signal processor march 2000 82 lucent technologies inc. 10 timing characteristics for 3.0 v operation (continued) 10.6 bit input/output (bio) figure 17. write outputs followed by read inputs (cbit = immediate; a1 = sbit) figure 18. write outputs and test inputs (cbit = immediate) table 75. timing requirements for bio input read abbreviated reference parameter min max unit t27 iobit input setup time (valid to high) 15 ns t28 iobit input hold time (high to invalid) 0 ns table 76. timing characteristics for bio output abbreviated reference parameter min max unit t29 iobit output valid time (low to valid) 9 ns t144 iobit output hold time (low to invalid) 1 ns table 77. timing requirements for bio input test abbreviated reference parameter min max unit t141 iobit input setup time (valid to low) 15 ns t142 iobit input hold time (low to invalid) 0 ns cko iobit (input) t28 t27 valid output v i h v i l v o h v o l v o h v o l data input t29 t144 iobit (output) 5-4019 (f).a cko iobit (input) t142 t141 valid output v oh C v o lC test input t29 t144 iobit (output) v oh C v o lC v ih C v i lC 5-4019 (f).b
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 83 10 timing characteristics for 3.0 v operation (continued) 10.7 external memory interface the following timing diagrams, characteristics, and requirements do not apply to interactions with delayed external memory enables unless so stated. see the dsp1611/17/18/27 digital signal processor information manual for a detailed description of the external memory interface including other functional diagrams. * w = number of wait-states. figure 19. enable transition timing table 78. timing characteristics for external memory enables (erom, eramhi, io, eramlo) abbreviated reference parameter min max unit t33 cko to enable active (low to low) 0 4.5 ns t34 cko to enable inactive (low to high) C1 4 ns table 79. timing characteristics for delayed external memory enables (ioc = 0x000f) abbreviated reference parameter min max unit t33 cko to delayed enable active (low to low) t/2 t/2 + 7 ns cko enable t34 t33 w * = 0 v oh v ol v oh v ol 5-4020 (f).b
data sheet dsp1629 digital signal processor march 2000 84 lucent technologies inc. 10 timing characteristics for 3.0 v operation (continued) * w = number of wait-states. figure 20. external memory data read timing diagram table 80. timing characteristics for external memory access abbreviated reference parameter min max unit t127 enable width (low to high) t(1 + w) C 1.5 ns t128 address valid (enable low to valid) 2 ns table 81. timing requirements for external memory read (erom, eramhi, io, eramlo) abbreviated reference parameter min max unit t129 read data setup (valid to enable high) 12 ns t130 read data hold (enable high to hold) 0 ns t150 external memory access time (valid to valid) t(1 + w) C 13 ns v ih v il db cko ab v oh v ol t128 read address enable v oh v ol v oh v ol (mwait = 0 x 2222) w* = 2 t127 t129 t130 read data t150 5-4021 (f).a
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 85 10 timing characteristics for 3.0 v operation (continued) * w = number of wait-states. figure 21. external memory data write timing diagram table 82. timing characteristics for external memory data write (all enables) abbreviated reference parameter min max unit t131 write overlap (enable low to 3-state) 0 ns t132 rwn advance (rwn high to enable high) 0 ns t133 rwn delay (enable low to rwn low) 0 ns t134 write data setup (data valid to rwn high) t(1 + w)/2 C 3 ns t135 rwn width (low to high) t(1 + w) C 4 ns t136 write address setup (address valid to rwn low) 0 ns eramlo erom cko ab rwn db write address read address v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol write data read w* = 1 t131 t132 t134 t133 t135 t136 (mwait = 0x1002) w* = 2 v oh v ol 5-4022 (f).a
data sheet dsp1629 digital signal processor march 2000 86 lucent technologies inc. 10 timing characteristics for 3.0 v operation (continued) * w = number of wait-states. figure 22. write cycle followed by read cycle table 83. timing characteristics for write cycle followed by read cycle abbreviated reference parameter min max unit t131 write overlap (enable low to 3-state) 0 ns t137 write data 3-state (rwn high to 3-state) 2 ns t138 write data hold (rwn high to data hold) 0 ns t139 write address hold (rwn high to address hold) 0 ns eramlo cko ab rwn write address read address v oh v ol v oh v ol v oh v ol v oh v ol w* = 1 t137 (mwait = 0x1002) w* = 2 erom v oh v ol db write read v oh v ol t138 t139 t131 5-4023 (f).a
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 87 10 timing characteristics for 3.0 v operation (continued) 10.8 phif specifications for the phif, read means read by the external user (output by the dsp); write is similarly defined. the 8-bit reads/writes are identical to one-half of a 16-bit access. figure 23. phif intel mode signaling (read and write) timing diagram * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pids and pods signals. an output transaction (read) is initiated by pcsn or pods going low, wh ichever comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pods going low, i f pods goes low after pcsn. an output transaction is completed by pcsn or pods going high, whichever comes first. an input transaction is initi ated by pcsn or pids going low, whichever comes last. an input transaction is completed by pcsn or pids going high, whichever comes first. all requirements referenced to pcsn apply to pids or pods, if pids or pods is the controlling signal. table 84. timing requirements for phif intel mode signaling abbreviated reference parameter min max unit t41 pods to pcsn setup (low to low) 0 ns t42 pcsn to pods hold (high to high) 0 ns t43 pids to pcsn setup (low to low) 0 ns t44 pcsn to pids hold (high to high) 0 ns t45* pstat to pcsn setup (valid to low) 4 ns t46* pcsn to pstat hold (high to invalid) 0 ns t47* pbsel to pcsn setup (valid to low) 6 ns t48* pcsn to pbsel hold (high to invalid) 0 ns t51* pb write to pcsn setup (valid to high) 10 ns t52* pcsn to pb write hold (high to invalid) 4 ns table 85. timing characteristics for phif intel mode signaling abbreviated reference parameter min max unit t49 * * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pids and pods signals. an output transaction (read) is initiated by pcsn or pods going low, whichever comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pods going low, if pods goes low after pcsn. an output transaction is completed by pcsn or pods going high, whichever comes first. an input transaction is initiated by pcsn or pids going low, whichever comes last. an input transaction is completed by pcsn or pids going high, whichever comes first. all requirements referenced to pcsn apply to pids or pods, if pids or pods is the controlling signal. pcsn to pb read (low to valid) 12 ns t50* pcsn to pb read hold (high to invalid) 0 ns t154 pcsn to pb read 3-state (high to 3-state) 8 ns 5-4036 (f) pcsn t41 t42 t43 t45 t46 t49 t50 16-bit read 16-bit write pods pids pbsel pstat pb[7:0] t47 t51 t52 t48 t44 t154 v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC
data sheet dsp1629 digital signal processor march 2000 88 lucent technologies inc. 10 timing characteristics for 3.0 v operation (continued) figure 24. phif intel mode signaling (pulse period and flags) timing diagram table 86. timing requirements for phif intel mode signaling abbreviated reference parameter min max unit t55 pcsn/pods/pids pulse width (high to low) 20.5 ns t56 pcsn/pods/pids pulse width (low to high) 20.5 ns table 87. timing characteristics for phif intel mode signaling abbreviated reference parameter min max unit t53 * * t53 should be referenced to the rising edge of pcsn or pods, whichever comes first. t54 should be referenced to the rising edge of pcsn or pids, whichever comes first. pcsn/pods to pobe ? (high to high) ? pobe and pibf may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 an d t54 apply to the inverted levels as well as those shown. 17ns t54* pcsn/pids to pibf ? (high to high) 17ns pods pids v ih v il v ih v il v ih v il t55 t56 t55 t56 t55 t56 pcsn t53 t54 16-bit read 8-bit write pbsel pobe pibf t54 v oh v ol v oh v ol v oh v ol t56 t56 t55 t53 8-bit read 16-bit write 5-4037 (f).a
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 89 10 timing characteristics for 3.0 v operation (continued) figure 25. phif motorola mode signaling (read and write) timing diagram * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pds signal. an input/output transaction is initiated by pcsn or pds going low, whichev er comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pds going low, if pds g oes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referen ced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transac tion. ? pds is programmable to be active-high or active-low. it is shown active-low in figures 49 and 50. pobe and pibf may be program med to be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pds signal. an input/output transaction is initiated by pcsn or pds going low, whichev er comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pds going low, if pds g oes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referen ced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transac tion. table 88. timing requirements for phif motorola mode signaling abbreviated reference parameter min max unit t41 pds ? to pcsn setup (valid to low) 0ns t42 pcsn to pds ? hold (high to invalid) 0ns t43 prwn to pcsn setup (valid to low) 4 ns t44 pcsn to prwn hold (high to invalid) 0 ns t45* pstat to pcsn setup (valid to low) 4 ns t46* pcsn to pstat hold (high to invalid) 0 ns t47* pbsel to pcsn setup (valid to low) 6 ns t48* pcsn to pbsel hold (high to invalid) 0 ns t51* pb write to pcsn setup (valid to high) 10 ns t52* pcsn to pb write hold (high to invalid) 4 ns table 89. timing characteristics for phif motorola mode signaling abbreviated reference parameter min max unit t49* pcsn to pb read (low to valid) 12 ns t50* pcsn to pb read hold (high to invalid) 0 ns t154 pcsn to pb read 3-state (high to 3-state) 8 ns pcsn pds prwn pbsel pstat pb[7:0] t41 t42 t43 t44 t45 t46 t47 t48 t52 t51 t50 t49 16-bit read 16-bit write t43 t44 v ih v il v ih v il v ih v il v ih v il v ih v il t154 5-4038 (f).a
data sheet dsp1629 digital signal processor march 2000 90 lucent technologies inc. 10 timing characteristics for 3.0 v operation (continued) figure 26. phif motorola mode signaling (pulse period and flags) timing diagram * an input/output transaction is initiated by pcsn or pds going low, whichever comes last. for example, t53 and t54 should be r eferenced to pds going low, if pds goes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referenced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transaction. ? pds is programmable to be active-high or active-low. it is shown active-low in figures 49 and 50. pobe and pibf may be program med to be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. table 90. timing characteristics for phif motorola mode signaling abbreviated reference parameter min max unit t53* pcsn/pds ? to pobe ? (high to high) 17ns t54* pcsn/pds ? to pibf ? (high to high) 17ns table 91. timing requirements for phif motorola mode signaling abbreviated reference parameter min max unit t55 pcsn/pds/prwn pulse width (high to low) 20 ns t56 pcsn/pds/prwn pulse width (low to high) 20 ns 5-4039 (f).a pds pids v ih C t55 t56 t55 t56 t55 t56 pcsn t53 t54 16-bit read 8-bit write pbsel pobe pibf t54 t56 t56 t55 t53 8-bit read 16-bit write v il C v ih C v il C v ih C v il C v oh C v ol C v oh C v ol C v oh C v ol C
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 91 10 timing characteristics for 3.0 v operation (continued) * motorola mode signal name. figure 27. phif intel or motorola mode signaling (status register read) timing diagram ? t45, t47, and t49 are referenced to the falling edge of pcsn or pods(pds), whichever occurs last. ? t46, t48, and t50 are referenced to the rising edge of pcsn or pods(pds), whichever occurs first. ? t45, t47, and t49 are referenced to the falling edge of pcsn or pods(pds), whichever occurs last. ? t46, t48, t154, and t50 are referenced to the rising edge of pcsn or pods(pds), whichever occurs first. table 92. timing requirements for intel and motorola mode signaling (status register read) abbreviated reference parameter min max unit t45 ? pstat to pcsn setup (valid to low) 4 ns t46 ? pcsn to pstat hold (high to invalid) 0 ns t47 ? pbsel to pcsn setup (valid to low) 6 ns t48 ? pcsn to pbsel hold (high to invalid) 0 ns table 93. timing characteristics for intel and motorola mode signaling (status register read) abbreviated reference parameter min max unit t49 ? pcsn to pb read (low to valid) 12 ns t50 ? pcsn to pb read hold (high to invalid) 0 ns t154 pcsn to pb read 3-state (high to 3-state) 8 ns pcsn pods (pds*) pids (prwn*) pbsel pstat pb[7:0] t47 t48 t45 t46 t49 t50 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il 5-4040 (f).a t154
data sheet dsp1629 digital signal processor march 2000 92 lucent technologies inc. 10 timing characteristics for 3.0 v operation (continued) figure 28. phif, pibf, and pobe reset timing diagram * after reset, pobe and pibf always go to the levels shown, indicating output buffer empty and input buffer empty. the dsp progr am, however, may later invert the definition of the logic levels for pobe and pibf. t57 and t58 continue to apply. ? pobe and pibf can be programmed to be active-high or active-low. they are shown active-high. the timing characteristic for act ive-low is the same as for active-high . figure 29. phif, pibf, and pobe disable timing diagram table 94. phif timing characteristics for phif, pibf, and pobe reset abbreviated reference parameter min max unit t57 rstb disable to pobe/pibf* (high to valid) 25 ns t58 rstb enable to pobe/pibf* (low to invalid) 3 25 ns table 95. phif timing characteristics for pobe and pibf disable abbreviated reference parameter min max unit t59 cko to pobe/pibf disable (high/low to disable) 20 ns rstb v ih C t58 t57 v il C pobe v oh C v ol C pibf v oh C v ol C 5-4775 (f) cko v ih C v il C t59 t59 pobe ? v oh C v ol C pibf ? v oh C v ol C 5-4776 (f)
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 93 10 timing characteristics for 3.0 v operation (continued) 10.9 serial i/o specifications * n = 16 or 8 bits. figure 30. sio passive mode input timing diagram ? for multiprocessor mode, see note in section 11.10. ? device is fully static; t70 is tested at 200 ns. table 96. timing requirements for serial inputs abbreviated reference parameter min max unit t70 clock period (high to high) ? 40 ? ns t71 clock low time (low to high) 18 ns t72 clock high time (high to low) 18 ns t73 load high setup (high to high) 8 ns t74 load low setup (low to high) 8 ns t75 load high hold (high to invalid) 0 ns t77 data setup (valid to high) 7 ns t78 data hold (high to invalid) 0 ns table 97. timing characteristics for serial outputs abbreviated reference parameter min max unit t79 ibf delay (high to high) 35 ns ibf v oh C v ol C di v ih C v il C ild v ih C v il C ick v ih C v il C bn C 1* b0 t77 t78 b0 b1 t79 t72 t71 t70 t75 t74 t75 t73 5-4777 (f)
data sheet dsp1629 digital signal processor march 2000 94 lucent technologies inc. 10 timing characteristics for 3.0 v operation (continued) * ild goes high during bit 6 (of 0:15), n = 8 or 16. figure 31. sio active mode input timing diagram table 98. timing requirements for serial inputs abbreviated reference parameter min max unit t77 data setup (valid to high) 7 ns t78 data hold (high to invalid) 0 ns table 99. timing characteristics for serial outputs abbreviated reference parameter min max unit t76a ild delay (high to low) 35 ns t101 ild hold (high to invalid) 3 ns t79 ibf delay (high to high) 35 ns ibf v oh C v ol C di v ih C v il C ild v oh C v ol C ick v oh C v ol C bn C 1 b0 t77 t78 b0 b1 t79 t101 t76a * 5-4778 (f)
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 95 10 timing characteristics for 3.0 v operation (continued) * see sioc register, msb field, to determine if b0 is the msb or lsb. see sioc register, ilen field, to determine if the do word length is 8 bits or 16 bits. figure 32. sio passive mode output timing diagram ? for multiprocessor mode, see note in section 11.10. ? device is fully static; t80 is tested at 200 ns. table 100. timing requirements for serial inputs abbreviated reference parameter min max unit t80 clock period (high to high) ? 40 ? ns t81 clock low time (low to high) 18 ns t82 clock high time (high to low) 18 ns t83 load high setup (high to high) 8 ns t84 load low setup (low to high) 8 ns t85 load hold (high to invalid) 0 ns table 101. timing characteristics for serial outputs abbreviated reference parameter min max unit t87 data delay (high to valid) 35 ns t88 enable data delay (low to active) 35 ns t89 disable data delay (high to 3-state) 35 ns t90 data hold (high to invalid) 3 ns t92 address delay (high to valid) 35 ns t93 address hold (high to invalid) 3 ns t94 enable delay (low to active) 35 ns t95 disable delay (high to 3-state) 35 ns t96 obe delay (high to high) 35 ns doen v ih C v il C sadd v oh C v ol C old v ih C v il C ock v ih C v il C t85 t80 t81 t82 t84 t83 t85 t88 b0 b1 b7 bn C 1 t90 t90 t87 t94 ad0 ad1 ad7 t93 t93 t92 as7 t89 t95 obe v oh C v ol C do* v oh C v ol C t96 5-4796 (f)
data sheet dsp1629 digital signal processor march 2000 96 lucent technologies inc. 10 timing characteristics for 3.0 v operation (continued) * old goes high at the end of bit 6 of 0:15. figure 33. sio active mode output timing diagram table 102. timing characteristics for serial output abbreviated reference parameter min max unit t86a old delay (high to low) 35 ns t102 old hold (high to invalid) 3 ns t87 data delay (high to valid) 35 ns t88 enable data delay (low to active) 35 ns t89 disable data delay (high to 3-state) 35 ns t90 data hold (high to invalid) 3 ns t92 address delay (high to valid) 35 ns t93 address hold (high to invalid) 3 ns t94 enable delay (low to active) 35 ns t95 disable delay (high to 3-state) 35 ns t96 obe delay (high to high) 35 ns doen v ih C v il C sadd v oh C v ol C old v oh C v ol C ock v oh C v ol C t102 t86a t88 b0 b1 b7 bn C 1 t90 t90 t87 t94 ad0 ad1 ad7 t93 t93 t92 as7 t89 t95 obe v oh C v ol C do v oh C v ol C t96 * 5-4797 (f)
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 97 10 timing characteristics for 3.0 v operation (continued) * see sioc register, ld field. figure 34. serial i/o active mode clock timing table 103. timing characteristics for signal generation abbreviated reference parameter min max unit t97 ick delay (high to high) 18 ns t98 ick delay (high to low) 18 ns t99 ock delay (high to high) 18 ns t100 ock delay (high to low) 18 ns t76a ild delay (high to low) 35 ns t76b ild delay (high to high) 35 ns t101 ild hold (high to invalid) 3 ns t86a old delay (high to low) 35 ns t86b old delay (high to high) 35 ns t102 old hold (high to invalid) 3 ns t103 sync delay (high to low) 35 ns t104 sync delay (high to high) 35 ns t105 sync hold (high to invalid) 3 ns ick v oh C v ol C cko v oh C v ol C t97 ock v oh C v ol C ick/ock* v oh C ild v oh C v ol C old v oh C v ol C sync v oh C v ol C t99 t98 t100 t101 t76a t101 t76b t102 t86a t102 t86b t105 t103 t105 t104 5-4798 (f)
data sheet dsp1629 digital signal processor march 2000 98 lucent technologies inc. 10 timing characteristics for 3.0 v operation (continued) 10.10 multiprocessor communication * negative edge initiates time slot 0. figure 35. sio multiprocessor timing diagram note: all serial i/o timing requirements and characteristics still apply, but the minimum clock period in passive multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2. ? with capacitance load on ick, ock, do, sync, and sadd = 100 pf, add 4 ns to t116t122. table 104. timing requirements for sio multiprocessor communication abbreviated reference parameter min max unit t112 sync setup (high/low to high) 35 ns t113 sync hold (high to high/low) 0 ns t114 address setup (valid to high) 12 ns t115 address hold (high to invalid) 0 ns table 105. timing characteristics for sio multiprocessor communication abbreviated reference ? parameter min max unit t116 data delay (bit 0 only) (low to valid) 35 ns t117 data disable delay (high to 3-state) 30 ns t120 doen valid delay (high to valid) 25 ns t121 address delay (bit 0 only) (low to valid) 35 ns t122 address disable delay (high to 3-state) 30 ns ock/ick b0 b15 b8 b7 b1 b0 b15 sync v ih C v il C do/d1 v oh C v ol C doen v oh C v ol C t112 t113 t112 t113 time slot 1 time slot 2 t117 t116 ad0 as7 as0 ad7 ad1 ad0 sadd t122 t121 t114 t115 t120 t120 * 5-4799 (f)
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 99 11 timing characteristics for 2.7 v operation the following timing characteristics and requirements are preliminary information and are subject to change. timing characteristics refer to the behavior of the device under specified conditions. timing requirements refer to conditions imposed on the user for proper operation of the device. all timing data is valid for the following conditions: t a = C40 c to +85 c (see section 8.3.) v dd = 3 v 10%, v ss = 0 v (see section 8.3.) capacitance load on outputs (c l ) = 50 pf, except for cko, where c l = 20 pf. output characteristics can be derated as a function of load capacitance (c l ). all outputs: 0.03 ns/pf dt/dc l 0.07 ns/pf for 10 c l 100 pf at v ih for rising edge and at v il for falling edge. for example, if the actual load capacitance is 30 pf instead of 50 pf, the derating for a rising edge is (30 C 50) pf x 0.06 ns/pf = 1.2 ns less than the specified rise time or delay that includes a rise time. test conditions for inputs: n rise and fall times of 4 ns or less n timing reference levels for delays = v ih , v il test conditions for outputs (unless noted otherwise): n c load = 50 pf; except for cko, where c load = 20 pf n timing reference levels for delays = v ih , v il n 3-state delays measured to the high-impedance state of the output driver for the timing diagrams, see table 62 for input clock requirements. unless otherwise noted, cko in the timing diagrams is the free-running cko.
data sheet dsp1629 digital signal processor march 2000 100 lucent technologies inc. 11 timing characteristics for 2.7 v operation (continued) 11.1 dsp clock generation * see table 62 for input clock electrical requirements. ? free-running clock. ? wait-stated clock (see table 38). w = number of wait-states. figure 36. i/o clock timing diagram ? device speeds greater than 50 mips do not support 1x operation. use the pll. ? device is fully static, t1 is tested at 100 ns for 1x input clock option, and memory hold time is tested at 0.1 s. ? t = internal clock period, set by cki or by cki and the pll parameters. table 106. timing requirements for input clock abbreviated reference parameter 19.2 ns and 12.5 ns ? min max unit t1 clock in period (high to high) 20 ? ns t2 clock in low time (low to high) 10 ns t3 clock in high time (high to low) 10 ns table 107. timing characteristics for input clock and output clock abbreviated reference parameter 19.2 ns 12.5 ns unit min max min max t4 clock out high delay 14 10 ns t5 clock out low delay (high to low) 14 10 ns t6 clock out period (low to low) t ? t ? ns t6a clock out period with slowcki bit set in powerc register (low to low) 0.74 3.8 0.74 3.8 m s 5-4009 (f).a t4 t1 t2 1x cki* t5 cko ? t3 t6, t6a cko ? external memory cycle w = 1
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 101 11 timing characteristics for 2.7 v operation (continued) 11.2 reset circuit the dsp1629 has two external reset pins: rstb and trst. at initial powerup, or if the supply voltage falls below v dd min* and a device reset is required, both trst and rstb must be asserted to initialize the device. figure 37 shows two separate events: n chip reset at initial powerup. n chip reset following a drop in power supply. note: the trst pin must be asserted even if the jtag controller is not used by the application. * see table 60, recommended operating conditions. * when both int0 and rstb are asserted, all output and bidirectional pins (except tdo, which 3-states by jtag control) are put i n a 3-state condition. with rstb asserted and int0 not asserted, erom, eramhi, eramlo, io, and rwn outputs remain high, and cko remains a free-running clock. ? see table 62 for input clock electrical requirements. figure 37. powerup reset and chip reset timing diagram note: the device needs to be clocked for at least six cki cycles during reset after powerup. otherwise, high cur- rents may flow. table 108. timing requirements for powerup reset and chip reset abbreviated reference parameter min max unit t8 rstb and trst reset pulse (low to high) 6t ns t9 v dd ramp 10 ms t146 v dd min to rstb low cmos small-signal 2t ns s t153 rstb (low to high) 54 ns table 109. timing characteristics for powerup reset and chip reset abbreviated reference parameter min max unit t10 rstb disable time (low to 3-state) 100 ns t11 rstb enable time (high to valid) 100 ns v dd ramp rstb, trst output pins* cki ? t11 v oh v ol v ih v il t9 t146 t10 0.4 v v dd min t11 v dd min 0.4 v t10 t9 t146 t153 t8 t153 t8 5-4010 (f).a
data sheet dsp1629 digital signal processor march 2000 102 lucent technologies inc. 11 timing characteristics for 2.7 v operation (continued) 11.3 reset synchronization * see table 62 for input clock electrical requirements. notes: cko 1 and cko 2 are two possible cko states before reset. cko is free-running. if the rising edge of rstb (low to high) is captured instead by the falling edge of cko (high to low), cko and cki will be in-p hase at t5 + 2 x t6. figure 38. reset synchronization timing table 110. timing requirements for reset synchronization timing abbreviated reference parameter min max unit t126 reset setup (high to high) 3 t/2 C 1 ns 5-4011 (f).a cki * v ih v il t126 t5 + 2 x t6 rstb v ih v il v ih v il cko v ih v il cko
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 103 11 timing characteristics for 2.7 v operation (continued) 11.4 jtag i/o specifications figure 39. jtag timing diagram table 111. timing requirements for jtag input/output abbreviated reference parameter min max unit t12 tck period (high to high) 50 ns t13 tck high time (high to low) 22.5 ns t14 tck low transition time (low to high) 22.5 ns t155 tck rise transition time (low to high) 0.6 v/ns t156 tck fall transition time (high to low) 0.6 v/ns t15 tms setup time (valid to high) 7.5 ns t16 tms hold time (high to invalid) 2 ns t17 tdi setup time (valid to high) 7.5 ns t18 tdi hold time (high to invalid) 2 ns table 112. timing characteristics for jtag input/output abbreviated reference parameter min max unit t19 tdo delay (low to valid) 19 ns t20 tdo hold (low to invalid) 0 ns t12 t14 t13 t15 t16 t17 t18 t19 t20 tck tms tdi tdo v ih v il v ih v il v ih v il v oh v ol t155 t156 5-4017 (f)
data sheet dsp1629 digital signal processor march 2000 104 lucent technologies inc. 11 timing characteristics for 2.7 v operation (continued) 11.5 interrupt * cko is free-running. ? iack assertion is guaranteed to be enclosed by vec[3:0] assertion. figure 40. interrupt timing diagram note: interrupt is asserted during an interruptible instruction and no other pending interrupts. note: interrupt is asserted during an interruptible instruction and no other pending interrupts. table 113. timing requirements for interrupt abbreviated reference parameter min max unit t21 interrupt setup (high to low) 19 ns t22 int assertion time (high to low) 2t ns table 114. timing characteristics for interrupt abbreviated reference parameter min max unit t23 iack assertion time (low to high) t/2 + 10 ns t24 vec assertion time (low to high) 12.5 ns t25 iack invalid time (low to low) 10 ns t26 vec invalid time (low to low) 12.5 ns 5-4018 (f) cko * int[1:0] t21 v oh v ol v ih v il t22 iack ? v oh v ol vec[3:0] v oh v ol t23 t24 t25 t26
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 105 11 timing characteristics for 2.7 v operation (continued) 11.6 bit input/output (bio) figure 41. write outputs followed by read inputs (cbit = immediate; a1 = sbit) figure 42. write outputs and test inputs (cbit = immediate) table 115. timing requirements for bio input read abbreviated reference parameter min max unit t27 iobit input setup time (valid to high) 15 ns t28 iobit input hold time (high to invalid) 0 ns table 116. timing characteristics for bio output abbreviated reference parameter min max unit t29 iobit output valid time (low to valid) 9 ns t144 iobit output hold time (low to invalid) 1 ns table 117. timing requirements for bio input test abbreviated reference parameter min max unit t141 iobit input setup time (valid to low) 15 ns t142 iobit input hold time (low to invalid) 0 ns 5-4019 (f).a cko iobit (input) t28 t27 valid output v i h v i l v o h v o l v o h v o l data input t29 t144 iobit (output) 5-4019 (f).b cko iobit (input) t142 t141 valid output v oh C v o lC test input t29 t144 iobit (output) v oh C v o lC v ih C v i lC
data sheet dsp1629 digital signal processor march 2000 106 lucent technologies inc. 11 timing characteristics for 2.7 v operation (continued) 11.7 external memory interface the following timing diagrams, characteristics, and requirements do not apply to interactions with delayed external memory enables unless so stated. see the dsp1611/17/18/27 digital signal processor information manual for a detailed description of the external memory interface including other functional diagrams. * w = number of wait-states. figure 43. enable transition timing table 118. timing characteristics for external memory enables (erom, eramhi, io, eramlo) abbreviated reference parameter min max unit t33 cko to enable active (low to low) 0 5 ns t34 cko to enable inactive (low to high) C1 4.5 ns table 119. timing characteristics for delayed external memory enables (ioc = 0x000f) abbreviated reference parameter min max unit t33 cko to delayed enable active (low to low) t/2 t/2 + 7 ns cko enable t34 t33 w * = 0 v oh v ol v oh v ol 5-4020 (f).b
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 107 11 timing characteristics for 2.7 v operation (continued) * w = number of wait-states. figure 44. external memory data read timing diagram table 120. timing characteristics for external memory access abbreviated reference parameter min max unit t127 enable width (low to high) t(1 + w) C 1.5 ns t128 address valid (enable low to valid) 2.5 ns table 121. timing requirements for external memory read (erom, eramhi, io, eramlo) abbreviated reference parameter 19.2 ns 12.5 ns unit min max min max t129 read data setup (valid to enable high) 15 13 ns t130 read data hold (enable high to hold) 0 0 ns t150 external memory access time (valid to valid) t(1 + w) C 15 t(1 + w) C 14 ns v ih v il db cko ab v oh v ol t128 read address enable v oh v ol v oh v ol (mwait = 0 x 2222) w* = 2 t127 t129 t130 read data t150 5-4021 (f).a
data sheet dsp1629 digital signal processor march 2000 108 lucent technologies inc. 11 timing characteristics for 2.7 v operation (continued) * w = number of wait-states. figure 45. external memory data write timing diagram table 122. timing characteristics for external memory data write (all enables) abbreviated reference parameter 19.2 ns 12.5 ns unit min max min max t131 write overlap (enable low to 3-state) 0 0 ns t132 rwn advance (rwn high to enable high) 0 0 ns t133 rwn delay (enable low to rwn low) 00ns t134 write data setup (data valid to rwn high) t(1 + w)/2 C 4 t(1 + w)/2 C 3 ns t135 rwn width (low to high) t(1 + w) C 5 t(1 + w) C 4 ns t136 write address setup (address valid to rwn low) 0 0 ns eramlo erom cko ab rwn db write address read address v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol write data read w* = 1 t131 t132 t134 t133 t135 t136 (mwait = 0x1002) w* = 2 v oh v ol 5-4022 (f).a
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 109 11 timing characteristics for 2.7 v operation (continued) * w = number of wait-states. figure 46. write cycle followed by read cycle table 123. timing characteristics for write cycle followed by read cycle abbreviated reference parameter min max unit t131 write overlap (enable low to 3-state) 0 ns t137 write data 3-state (rwn high to 3-state) 2 ns t138 write data hold (rwn high to data hold) 0 ns t139 write address hold (rwn high to address hold) 0 ns eramlo cko ab rwn write address read address v oh v ol v oh v ol v oh v ol v oh v ol w* = 1 t137 (mwait = 0x1002) w* = 2 erom v oh v ol db write read v oh v ol t138 t139 t131 5-4023 (f).a
data sheet dsp1629 digital signal processor march 2000 110 lucent technologies inc. 11 timing characteristics for 2.7 v operation (continued) 11.8 phif specifications for the phif, read means read by the external user (output by the dsp); write is similarly defined. the 8-bit reads/ writes are identical to one-half of a 16-bit access. figure 47. phif intel mode signaling (read and write) timing diagram * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pids and pods signals. an output transaction (read) is initiated by pcsn or pods going low, which- ever comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pods g oing low, if pods goes low after pcsn. an output transaction is completed by pcsn or pods going high, whichever comes first. an input tra nsaction is initiated by pcsn or pids going low, whichever comes last. an input transaction is completed by pcsn or pids going high, whi chever comes first. all requirements referenced to pcsn apply to pids or pods, if pids or pods is the controlling signal. * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pids and pods signals. an output transaction (read) is initiated by pcsn or pods going low, which- ever comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pods g oing low, if pods goes low after pcsn. an output transaction is completed by pcsn or pods going high, whichever comes first. an input tra nsaction is initiated by pcsn or pids going low, whichever comes last. an input transaction is completed by pcsn or pids going high, whi chever comes first. all requirements referenced to pcsn apply to pids or pods, if pids or pods is the controlling signal. table 124. timing requirements for phif intel mode signaling abbreviated reference parameter min max unit t41 pods to pcsn setup (low to low) 0 ns t42 pcsn to pods hold (high to high) 0 ns t43 pids to pcsn setup (low to low) 0 ns t44 pcsn to pids hold (high to high) 0 ns t45* pstat to pcsn setup (valid to low) 4 ns t46* pcsn to pstat hold (high to invalid) 0 ns t47* pbsel to pcsn setup (valid to low) 6 ns t48* pcsn to pbsel hold (high to invalid) 0 ns t51* pb write to pcsn setup (valid to high) 10 ns t52* pcsn to pb write hold (high to invalid) 4 ns table 125. timing characteristics for phif intel mode signaling abbreviated reference parameter min max unit t49* pcsn to pb read (low to valid) 12 ns t50* pcsn to pb read hold (high to invalid) 0 ns t154 pcsn to pb read 3-state (high to 3-state) 8 ns 5-4036 (f) pcsn t41 t42 t43 t45 t46 t49 t50 16-bit read 16-bit write pods pids pbsel pstat pb[7:0] t47 t51 t52 t48 t44 t154 v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC v ihC v ilC
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 111 11 timing characteristics for 2.7 v operation (continued) figure 48. phif intel mode signaling (pulse period and flags) timing diagram * t53 should be referenced to the rising edge of pcsn or pods, whichever comes first. t54 should be referenced to the rising edge of pcsn or pids, whichever comes first. ? pobe and pibf may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 an d t54 apply to the inverted levels as well as those shown. table 126. timing requirements for phif intel mode signaling abbreviated reference parameter min max unit t55 pcsn/pods/pids pulse width (high to low) 20.5 ns t56 pcsn/pods/pids pulse width (low to high) 20.5 ns table 127. timing characteristics for phif intel mode signaling abbreviated reference parameter min max unit t53* pcsn/pods to pobe ? (high to high) 17ns t54* pcsn/pids to pibf ? (high to high) 17ns pods pids v ih v il v ih v il v ih v il t55 t56 t55 t56 t55 t56 pcsn t53 t54 16-bit read 8-bit write pbsel pobe pibf t54 v oh v ol v oh v ol v oh v ol t56 t56 t55 t53 8-bit read 16-bit write 5-4037 (f).a
data sheet dsp1629 digital signal processor march 2000 112 lucent technologies inc. 11 timing characteristics for 2.7 v operation (continued) figure 49. phif motorola mode signaling (read and write) timing diagram * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pds signal. an input/output transaction is initiated by pcsn or pds going low, whichev er comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pds going low, if pds g oes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referen ced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transac tion. ? pds is programmable to be active-high or active-low. it is shown active-low in figures 49 and 50. pobe and pibf may be program med to be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. * this timing diagram for the phif port shows accesses using the pcsn signal to initiate and complete a transaction. the transac tions can also be initiated and completed with the pds signal. an input/output transaction is initiated by pcsn or pds going low, whichev er comes last. for example, the timing requirements referenced to pcsn going low, t45 and t49, should be referenced to pds going low, if pds g oes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever comes first. all requirements referen ced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transac tion. table 128. timing requirements for phif motorola mode signaling abbreviated reference parameter min max unit t41 pds ? to pcsn setup (valid to low) 0ns t42 pcsn to pds ? hold (high to invalid) 0ns t43 prwn to pcsn setup (valid to low) 4 ns t44 pcsn to prwn hold (high to invalid) 0 ns t45* pstat to pcsn setup (valid to low) 4 ns t46* pcsn to pstat hold (high to invalid) 0 ns t47* pbsel to pcsn setup (valid to low) 6 ns t48* pcsn to pbsel hold (high to invalid) 0 ns t51* pb write to pcsn setup (valid to high) 10 ns t52* pcsn to pb write hold (high to invalid) 4 ns table 129. timing characteristics for phif motorola mode signaling abbreviated reference parameter min max unit t49* pcsn to pb read (low to valid) 12 ns t50* pcsn to pb read hold (high to invalid) 0 ns t154 pcsn to pb read 3-state (high to 3-state) 8 ns pcsn pds prwn pbsel pstat pb[7:0] t41 t42 t43 t44 t45 t46 t47 t48 t52 t51 t50 t49 16-bit read 16-bit write t43 t44 v ih v il v ih v il v ih v il v ih v il v ih v il t154 5-4038 (f).a
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 113 11 timing characteristics for 2.7 v operation (continued) figure 50. phif motorola mode signaling (pulse period and flags) timing diagram * an input/output transaction is initiated by pcsn or pds going low, whichever comes last. for example, t53 and t54 should be r eferenced to pds going low, if pds goes low after pcsn. an input/output transaction is completed by pcsn or pds going high, whichever com es first. all requirements referenced to pcsn should be referenced to pds, if pds is the controlling signal. prwn should never be used to initiate or complete a transaction. ? pds is programmable to be active-high or active-low. it is shown active-low in figures 49 and 50. pobe and pibf may be program med to be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. table 130. timing characteristics for phif motorola mode signaling abbreviated reference parameter min max unit t53* pcsn/pds ? to pobe ? (high to high) 17ns t54* pcsn/pds ? to pibf ? (high to high) 17ns table 131. timing requirements for phif motorola mode signaling abbreviated reference parameter min max unit t55 pcsn/pds/prwn pulse width (high to low) 20 ns t56 pcsn/pds/prwn pulse width (low to high) 20 ns pds prwn v ih C t55 t56 t55 t56 t55 t56 pcsn t53 t54 16-bit read 8-bit write pbsel pobe pibf t54 t56 t56 t55 t53 8-bit read 16-bit write v il C v ih C v il C v ih C v il C v oh C v ol C v oh C v ol C v oh C v ol C 5-4039 (f).a
data sheet dsp1629 digital signal processor march 2000 114 lucent technologies inc. 11 timing characteristics for 2.7 v operation (continued) * motorola mode signal name. figure 51. phif intel or motorola mode signaling (status register read) timing diagram ? t45, t47, and t49 are referenced to the falling edge of pcsn or pods(pds), whichever occurs last. ? t46, t48, and t50 are referenced to the rising edge of pcsn or pods(pds), whichever occurs first. ? t45, t47, and t49 are referenced to the falling edge of pcsn or pods(pds), whichever occurs last. ? t46, t48, and t50 are referenced to the rising edge of pcsn or pods(pds), whichever occurs first. table 132. timing requirements for intel and motorola mode signaling (status register read) abbreviated reference parameter min max unit t45 ? pstat to pcsn setup (valid to low) 4 ns t46 ? pcsn to pstat hold (high to invalid) 0 ns t47 ? pbsel to pcsn setup (valid to low) 6 ns t48 ? pcsn to pbsel hold (high to invalid) 0 ns table 133. timing characteristics for intel and motorola mode signaling (status register read) abbreviated reference parameter min max unit t49 ? pcsn to pb read (low to valid) 12 ns t50 ? pcsn to pb read hold (high to invalid) 0 ns t154 pcsn to pb read 3-state (high to 3-state) 8 ns pcsn pods (pds*) pids (prwn*) pbsel pstat pb[7:0] t47 t48 t45 t46 t49 t50 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il 5-4040 (f).a t154
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 115 11 timing characteristics for 2.7 v operation (continued) figure 52. phif, pibf, and pobe reset timing diagram * after reset, pobe and pibf always go to the levels shown, indicating output buffer empty and input buffer empty. the dsp progr am, however, may later invert the definition of the logic levels for pobe and pibf. t57 and t58 continue to apply. ? pobe and pibf can be programmed to be active-high or active-low. they are shown active-high. the timing characteristic for act ive-low is the same as for active-high . figure 53. phif, pibf, and pobe disable timing diagram table 134. phif timing characteristics for phif, pibf, and pobe reset abbreviated reference parameter min max unit t57 rstb disable to pobe/pibf* (high to valid) 25 ns t58 rstb enable to pobe/pibf* (low to invalid) 3 25 ns table 135. phif timing characteristics for pobe and pibf disable abbreviated reference parameter min max unit t59 cko to pobe/pibf disable (high/low to disable) 20 ns rstb v ih C t58 t57 v il C pobe v oh C v ol C pibf v oh C v ol C 5-4775 (f) cko v ih C v il C t59 t59 pobe ? v oh C v ol C pibf ? v oh C v ol C 5-4776 (f)
data sheet dsp1629 digital signal processor march 2000 116 lucent technologies inc. 11 timing characteristics for 2.7 v operation (continued) 11.9 serial i/o specifications * n = 16 or 8 bits. figure 54. sio passive mode input timing diagram ? for multiprocessor mode, see note in section 11.10. ? device is fully static; t70 is tested at 200 ns. table 136. timing requirements for serial inputs abbreviated reference parameter min max unit t70 clock period (high to high) ? 40 ? ns t71 clock low time (low to high) 18 ns t72 clock high time (high to low) 18 ns t73 load high setup (high to high) 8 ns t74 load low setup (low to high) 8 ns t75 load high hold (high to invalid) 0 ns t77 data setup (valid to high) 7 ns t78 data hold (high to invalid) 0 ns table 137. timing characteristics for serial outputs abbreviated reference parameter min max unit t79 ibf delay (high to high) 35 ns ibf v oh C v ol C di v ih C v il C ild v ih C v il C ick v ih C v il C bn C 1* b0 t77 t78 b0 b1 t79 t72 t71 t70 t75 t74 t75 t73 5-4777 (f)
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 117 11 timing characteristics for 2.7 v operation (continued) * ild goes high during bit 6 (of 0:15), n = 8 or 16. figure 55. sio active mode input timing diagram table 138. timing requirements for serial inputs abbreviated reference parameter min max unit t77 data setup (valid to high) 7 ns t78 data hold (high to invalid) 0 ns table 139. timing characteristics for serial outputs abbreviated reference parameter min max unit t76a ild delay (high to low) 35 ns t101 ild hold (high to invalid) 3 ns t79 ibf delay (high to high) 35 ns ibf v oh C v ol C di v ih C v il C ild v oh C v ol C ick v oh C v ol C bn C 1 b0 t77 t78 b0 b1 t79 t101 t76a * 5-4778 (f)
data sheet dsp1629 digital signal processor march 2000 118 lucent technologies inc. 11 timing characteristics for 2.7 v operation (continued) * see sioc register, msb field, to determine if b0 is the msb or lsb. see sioc register, ilen field, to determine if the do word length is 8 bits or 16 bits. figure 56. sio passive mode output timing diagram ? for multiprocessor mode, see note in section 11.10. ? device is fully static; t80 is tested at 200 ns. table 140. timing requirements for serial inputs abbreviated reference parameter min max unit t80 clock period (high to high) ? 40 ? ns t81 clock low time (low to high) 18 ns t82 clock high time (high to low) 18 ns t83 load high setup (high to high) 8 ns t84 load low setup (low to high) 8 ns t85 load hold (high to invalid) 0 ns table 141. timing characteristics for serial outputs abbreviated reference parameter min max unit t87 data delay (high to valid) 35 ns t88 enable data delay (low to active) 35 ns t89 disable data delay (high to 3-state) 35 ns t90 data hold (high to invalid) 3 ns t92 address delay (high to valid) 35 ns t93 address hold (high to invalid) 3 ns t94 enable delay (low to active) 35 ns t95 disable delay (high to 3-state) 35 ns t96 obe delay (high to high) 35 ns doen v ih C v il C sadd v oh C v ol C old v ih C v il C ock v ih C v il C t85 t80 t81 t82 t84 t83 t85 t88 b0 b1 b7 bn C 1 t90 t90 t87 t94 ad0 ad1 ad7 t93 t93 t92 as7 t89 t95 obe v oh C v ol C do* v oh C v ol C t96 5-4796 (f)
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 119 11 timing characteristics for 2.7 v operation (continued) * old goes high at the end of bit 6 of 0:15. figure 57. sio active mode output timing diagram table 142. timing characteristics for serial output abbreviated reference parameter min max unit t86a old delay (high to low) 35 ns t102 old hold (high to invalid) 3 ns t87 data delay (high to valid) 35 ns t88 enable data delay (low to active) 35 ns t89 disable data delay (high to 3-state) 35 ns t90 data hold (high to invalid) 3 ns t92 address delay (high to valid) 35 ns t93 address hold (high to invalid) 3 ns t94 enable delay (low to active) 35 ns t95 disable delay (high to 3-state) 35 ns t96 obe delay (high to high) 35 ns doen v ih C v il C sadd v oh C v ol C old v oh C v ol C ock v oh C v ol C t102 t86a t88 b0 b1 b7 bn C 1 t90 t90 t87 t94 ad0 ad1 ad7 t93 t93 t92 as7 t89 t95 obe v oh C v ol C do v oh C v ol C t96 * 5-4797 (f)
data sheet dsp1629 digital signal processor march 2000 120 lucent technologies inc. 11 timing characteristics for 2.7 v operation (continued) * see sioc register, ld field. figure 58. serial i/o active mode clock timing table 143. timing characteristics for signal generation abbreviated reference parameter min max unit t97 ick delay (high to high) 18 ns t98 ick delay (high to low) 18 ns t99 ock delay (high to high) 18 ns t100 ock delay (high to low) 18 ns t76a ild delay (high to low) 35 ns t76b ild delay (high to high) 35 ns t101 ild hold (high to invalid) 3 ns t86a old delay (high to low) 35 ns t86b old delay (high to high) 35 ns t102 old hold (high to invalid) 3 ns t103 sync delay (high to low) 35 ns t104 sync delay (high to high) 35 ns t105 sync hold (high to invalid) 3 ns ick v oh C v ol C cko v oh C v ol C t97 ock v oh C v ol C ick/ock* v oh C ild v oh C v ol C old v oh C v ol C sync v oh C v ol C t99 t98 t100 t101 t76a t101 t76b t102 t86a t102 t86b t105 t103 t105 t104 5-4798 (f)
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 121 11 timing characteristics for 2.7 v operation (continued) 11.10 multiprocessor communication * negative edge initiates time slot 0. figure 59. sio multiprocessor timing diagram note: all serial i/o timing requirements and characteristics still apply, but the minimum clock period in passive multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2. ? with capacitance load on ick, ock, do, sync, and sadd = 100 pf, add 4 ns to t116t122. table 144. timing requirements for sio multiprocessor communication abbreviated reference parameter min max unit t112 sync setup (high/low to high) 35 ns t113 sync hold (high to high/low) 0 ns t114 address setup (valid to high) 12 ns t115 address hold (high to invalid) 0 ns table 145. timing characteristics for sio multiprocessor communication abbreviated reference ? parameter min max unit t116 data delay (bit 0 only) (low to valid) 35 ns t117 data disable delay (high to 3-state) 30 ns t120 doen valid delay (high to valid) 25 ns t121 address delay (bit 0 only) (low to valid) 35 ns t122 address disable delay (high to 3-state) 30 ns ock/ick b0 b15 b8 b7 b1 b0 b15 sync v ih C v il C do/d1 v oh C v ol C doen v oh C v ol C t112 t113 t112 t113 time slot 1 time slot 2 t117 t116 ad0 as7 as0 ad7 ad1 ad0 sadd t122 t121 t114 t115 t120 t120 * 5-4799 (f)
data sheet dsp1629 digital signal processor march 2000 122 lucent technologies inc. 12 outline diagrams 12.1 100-pin bqfp (bumpered quad flat pack) all dimensions are in millimeters. 5-1970 (f)r.10 pin #1 identifier zone 89 1 13 14 38 39 6 3 64 88 19.050 0.405 22.350 0.255 22.860 0.305 22.350 0.255 19.050 0.405 22.860 0.305 edge chamfer detail a 4.570 max detail b 0.760 0.255 0.635 typ 0.10 seating plane 3.555 0.255 detail b 0.280 0.075 0.150 m 0.175 0.025 detail a 0.255 0.91/1.17 gage plane seating plane
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 123 12 outline diagrams (continued) 12.2 100-pin tqfp (thin quad flat pack) all dimensions are in millimeters. 0.50 typ 1.60 max seating plane 0.08 1.40 0.05 0.05/0.15 detail a detail b 14.00 0.20 16.00 0.20 76 100 1 25 26 50 51 75 14.00 0.20 16.00 0.20 pin #1 identifier zone detail b 0.19/0.27 0.08 m 0.106/0.200 detail a 0.45/0.75 gage plane seating plane 1.00 ref 0.25 5-2146 (f)r.14
data sheet dsp1629 digital signal processor march 2000 124 lucent technologies inc. 12 outline diagrams (continued) 12.3 144-pin pbga (plastic ball grid array) all dimensions are in millimeters. 0.36 0.04 0.80 0.05 1.56 + 0.19 C 0.21 seating plane solder ball 0.40 0.10 0.20 pwb mold compound pin a1 corner 13.00 0.20 13.00 0.20 11.50 +0.70 C0.00 11.50 +0.70 C0.00 a b c d e f g h j k l m 123456789101112 11 spaces @ 1.00 = 11.00 pin a1 corner 11 spaces @ 1.00 = 11.00 0.50 0.10 5-5205 (f)
data sheet march 2000 dsp1629 digital signal processor lucent technologies inc. 125 notes
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. copyright ? 2000 lucent technologies inc. all rights reserved march 2000 ds00-206wtec (replaces ds00-062wtec) for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18103 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 316 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries:germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 4354 2800 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)

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